Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated
System Interconnect
97
SPRS689D—March 2012
TMS320C6670
4.4 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority
registers will be present to allow software configuration of the data traffic through the TeraNet. Note that a lower
number means higher priority - PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. Examples include the
CorePacs, whose priorities are set through software in the UMC control registers. All the Packet DMA based
peripherals also have internal registers to define the priority level of their initiated transactions.
The Packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The
priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in
.
For all other modules, see the respective User Guides in
2.9 ‘‘Related Documentation from Texas Instruments’’ on
for programmable priority registers.
Figure 4-7
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
31
3
2
0
Reserved
PKTDMA_PRI
R/W-00000000000000000000001000011
RW-000
Legend: R = Read only; R/W = Read/Write; -
n
= value after reset
Table 4-4
Packed DMA Priority Allocation Register Field Descriptions
Bit
Field
Description
31-3
Reserved
Reserved.
2-0
PKDTDMA_PRI
Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.
End of Table 4-4
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