Texas Instruments TMS320C6670, Data Manual

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136 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
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7.5.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value
is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG
is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register
(RSTCTRL) is shown in
Figure 7-14 and described in Table 7-21 .
7.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, the watchdog timer, and the PLL Controller’s
RSTCTRL Register; i.e., a hard reset or a soft reset. By default, these resets are hard resets. The Reset Configuration
Register (RSTCFG) is shown in
Figure 7-15 and described in Table 7-22 .
Figure 7-14 Reset Control Register (RSTCTRL)
31 17 16 15 0
Reserved SWRST KEY
R-0x0000 R/W-0x
(1)
1 Writes are conditional based on valid key.
R/W-0x0003
Legend: R = Read only; - n = value after reset;
Table 7-21 Reset Control Register Field Descriptions
Bit Field Description
31-17 Reserved Reserved
16 SWRST Software reset
0 = Reset
1 = Not reset
15-0 KEY Key used to enable writes to RSTCTRL and RSTCFG.
End of Table 7-21
Figure 7-15 Reset Configuration Register (RSTCFG)
31 16 15 14 13 12 11 4 3 0
Reserved Reserved PLLCTLRSTTYPE RESETTYPE Reserved WDTYPE[N
(1)
]
1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)
R-0x0000 R-00 R/W-0
(2)
2 Writes are conditional based on valid key. For details, see Section 7.5.2.7 ‘‘Reset Control Register (RSTCTRL)’’ .
R/W-0
2
R-0x0 R/W-0x00
2
Legend: R = Read only; R/W = Read/Write; - n = value after reset
Table 7-22 Reset Configuration Register Field Descriptions (Part 1 of 2)
Bit Field Description
31-14 Reserved Reserved
13 PLLCTLRSTTYPE PLL controller initiates a software-driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12 RESETTYPE RESET initiates a reset of type:
0 = Hard reset (default)
1 = Soft reset