Texas Instruments TMS320C6670, Data Manual

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128 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
www.ti.com
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7.5 Main PLL and the PLL Controller
This section provides a description of the Main PLL and the PLL Controller. For details on the operation of the PLL
Controller module, see the
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.9 ‘‘Related
Documentation from Texas Instruments’’ on page 66 .
The Main PLL is controlled by the standard PLL Controller. The PLL Controller manages the clock ratios,
alignment, and gating for the system clocks to the device.
Figure 7-7 shows a block diagram of the Main PLL and the
PLL Controller.
Figure 7-7 Main PLL and PLL Controller
S Y SCLK11
/6
PLLDIV11
To Switch Fabric,
Peripherals,
Accelerators
1
0
PLL Controller
/2
O UTPUT
DIVIDE
S Y SCLK8
/z
PLLDIV8
S Y SCLK2
/x
PLLDIV2
S Y SCLK3
/2
PLLDIV3
S Y SCLK4
/3
PLLDIV4
S Y SCLK5
/y
PLLDIV5
S Y SCLK6
/64
PLLDIV6
S Y SCLK 7
/6
PLLDIV 7
S Y SCLK9
/12
PLLDIV9
S Y SCLK10
/3
PLLDIV10
S Y SCLK ( N|P )
ALTCORECLK ( N|P )
CORECLKSEL
AIF Module
xPLLM PLLD
PLL
BYPASS
/2
O UTPUT
DIVIDE
C66x
CorePac
S Y SCLK1
/1
PLLDIV1
PLLOUT
1
0
1
0
0
PLLEN
PLLENSRC