Texas Instruments TMS320C6670, Data Manual

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210 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
www.ti.com
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7.21 Timers
The timers can be used to time events, count events, generate pulses, interrupt the CPU, and send synchronization
events to the EDMA3 channel controller.
7.21.1 Timers Device-Specific Information
The TMS320C6670 device has eight 64-bit timers in total. Of which Timer0 through Timer3 are dedicated to each
of the four CorePacs as a watchdog timer and can also be used as general-purpose timers. Each of other four timers
can also be configured as a general-purpose timer only, with each timer programmed as a 64-bit timer or as two
separate 32-bit timers.
When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge)
and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable
period. When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up
of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to
the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that
software writes to the timer before the count expires, after which the count begins again. If the count ever
reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming
‘‘Reset
Type Status Register (RSTYPE)’’ on page 135 and the type of reset initiated can set by programming ‘‘Reset
Configuration Register (RSTCFG)’’ on page 136. For more information, see the 64-bit Timer (Timer 64) for KeyStone
Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66.
7.21.2 Timers Electrical Data/Timing
The tables and figures below describe the timing requirements and switching characteristics of Timer0 - Timer7.
Figure 7-52 Timer Timing
Table 7-79 Timer Input Timing Requirements
(1)
(see Figure 7-52 )
1 C = 1/SYSCLK1 clock frequency in ns
No. Min Max Unit
1 t
w(TINPH)
Pulse duration, high 12C ns
2 t
w(TINPL)
Pulse duration, low 12C ns
End of Table 7-79
Table 7-80 Timer Output Switching Characteristics
(1)
(see Figure 7-52 )
1 C = 1/SYSCLK1 clock frequency in ns.
No. Parameter Min Max Unit
3 t
w(TOUTH)
Pulse duration, high 12C - 3 ns
4 t
w(TOUTL)
Pulse duration, low 12C - 3 ns
End of Table 7-80
TIMIx
1 2
TIM O x
3 4