Texas Instruments TMS320C6670, Data Manual

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Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications 133
SPRS689D—March 2012
TMS320C6670
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7.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, and PLLDIV8)
The PLL Controller Divider Registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in Figure 7-9 and described
in Table 7-16 . The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different
and mentioned in the footnote of Figure 7-9 .
7.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL Controller Clock Align Control Register (ALNCTL) is shown in Figure 7-10 and described in Table 7-17 .
Figure 7-9 PLL Controller Divider Register (PLLDIVn)
31 16 15 14 8 7 0
Reserved D n
(1)
EN
1 D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8
Reserved RATIO
R-0 R/W-1 R-0 R/W-n
(2)
2 n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8
Legend: R/W = Read/Write; R = Read only; - n = value after reset
Table 7-16 PLL Controller Divider Register Field Descriptions
Bit Field Description
31-16 Reserved Reserved
15 D n EN Divider D n enable bit (See footnote of Figure 7-9 )
0 = Divider n is disabled
1 = No clock output. Divider n is enabled.
14-8 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0 RATIO Divider ratio bits (See footnote of Figure 7-9
)
0h = ÷1. Divide frequency by 1
1h = ÷2. Divide frequency by 2
2h = ÷3. Divide frequency by 3
3h = ÷4. Divide frequency by 4
4h - 4Fh = ÷5 to ÷80. Divide frequency range: divide frequency by 5 to divide frequency by 80.
End of Table 7-16
Figure 7-10 PLL Controller Clock Align Control Register (ALNCTL)
31 8 7 6 5 4 3 2 1 0
Reserved ALN8 Reserved ALN5 Reserved ALN2 Reserved
R-0 R/W-1 R-0 R/W-1 R-0 R/W-1 R-0
Legend: R/W = Read/Write; R = Read only; - n = value after reset, for reset value
Table 7-17 PLL Controller Clock Align Control Register Field Descriptions
Bit Field Description
31-8
6-5
3-2
0
Reserved Reserved. This location is always read as 0. A value written to this field has no effect.
7
4
1
ALN8
ALN5
ALN2
SYSCLK n alignment. Do not change the default values of these fields.
0 = Do not align SYSCLK n to other SYSCLKs during GO operation. If SYS n in DCHANGE is set, SYSCLK n switches to the new
ratio immediately after the GOSET bit in PLLCMD is set.
1 = Align SYSCLK n to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYS n in DCHANGE is 1.
The SYSCLK n rate is set to the ratio programmed in the RATIO bit in PLLDIV n .
End of Table 7-17