Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
139
SPRS689D—March 2012
TMS320C6670
Note—
The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller
and the PLLM[12:6] bits are controlled by the above chip-level register. MAINPLLCTL0 register
PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to
have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide
“Related Documentation from Texas
for the recommended programming sequence. Output Divide ratio and Bypass
enable/disable of the Main PLL is also controlled by the SECCTL register in the PLL Controller. See the
Secondary Control Register (SECCTL)” on page 132
for more details.
7.5.4 Main PLL and PLL Controller Initialization Sequence
See the
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide
“Related Documentation from Texas
for details on the initialization sequence for Main PLL and PLL Controller.
7.5.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
Table 7-26
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
(1)
(see
and
No.
Min
Max
Unit
SYSCLK[P:N]
1
tc(SYSCLKN)
Cycle time SYSCLKN cycle time
3.25 or 6.51 or 8.138
(2)
ns
1
tc(SYSCLKP)
Cycle time SYSCLKP cycle time
3.25 or 6.51 or 8.138
ns
3
tw(SYSCLKN)
Pulse width SYSCLKN high
0.45*tc
0.55*tc
ns
2
tw(SYSCLKN)
Pulse width SYSCLKN low
0.45*tc
0.55*tc
ns
2
tw(SYSCLKP)
Pulse width SYSCLKP high
0.45*tc
0.55*tc
ns
3
tw(SYSCLKP)
Pulse width SYSCLKP low
0.45*tc
0.55*tc
ns
4
tr(SYSCLKN_250 mv)
Transition time SYSCLKN rise time (250 mV)
50
350
ps
4
tf(SYSCLKN_250 mv)
Transition time SYSCLKN fall time (250 mV)
50
350
ps
4
tr(SYSCLKP_250 mv)
Transition time SYSCLKP rise time (250 mV)
50
350
ps
4
tf(SYSCLKP_250 mv)
Transition time SYSCLKP fall time (250 mV)
50
350
ps
5
tj(SYSCLKN)
Jitter, peak_to_peak _ periodic SYSCLKN
100 (4
(3)
)
ps
5
tj(SYSCLKP)
Jitter, peak_to_peak _ periodic SYSCLKP
100 (4)
ps
ALTCORECLK[P:N]
1
tc(ALTCORCLKN)
Cycle time ALTCORECLKN cycle time
3.2
25
ns
1
tc(ALTCORECLKP)
Cycle time ALTCORECLKP cycle time
3.2
25
ns
3
tw(ALTCORECLKN)
Pulse width ALTCORECLKN high
0.45*tc(ALTCORECLKN)
0.55*tc(ALTCORECLKN)
ns
2
tw(ALTCORECLKN)
Pulse width ALTCORECLKN low
0.45*tc(ALTCORECLKN)
0.55*tc(ALTCORECLKN)
ns
2
tw(ALTCORECLKP)
Pulse width ALTCORECLKP high
0.45*tc(ALTCORECLKP)
0.55*tc(ALTCORECLKP)
ns
3
tw(ALTCORECLKP)
Pulse width ALTCORECLKP low
0.45*tc(ALTCORECLKP)
0.55*tc(ALTCORECLKP)
ns
4
tr(ALTCORECLKN_250 mv)
Transition time ALTCORECLKN rise time (250 mV)
50
350
ps
4
tf(ALTCORECLKN_250 mv)
Transition time ALTCORECLKN fall time (250 mV)
50
350
ps
4
tr(ALTCORECLKP_250 mv)
Transition time ALTCORECLKP rise time (250 mV)
50
350
ps
4
tf(ALTCORECLKP_250 mv)
Transition time ALTCORECLKP fall time (250 mV)
50
350
ps
5
tj(ALTCORECLKN)
Jitter, peak_to_peak _ periodic ALTCORECLKN
100
ps
5
tj(ALTCORECLKP)
Jitter, peak_to_peak _ periodic ALTCORECLKP
100
ps
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