Texas Instruments TMS320C6670, Data Manual

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182 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
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Table 7-51 shows the privilege ID of each CorePac and every mastering peripheral. Table 7-51 also shows the
privilege level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs.
data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being
executed at the time of the access or the configuration of the master peripheral.
7.10.1 MPU Registers
This section includes the offsets for MPU registers and definitions for device-specific MPU registers.
7.10.1.1 MPU Register Map
Table 7-51 Privilege ID Settings
Privilege ID Master Privilege Level Security Level Access Type
0 CorePac0 SW dependant, driven by MSMC SW dependant DMA
1 CorePac1 SW dependant, driven by MSMC SW dependant DMA
2 CorePac2 SW dependant, driven by MSMC SW dependant DMA
3 CorePac3 SW dependant, driven by MSMC SW dependant DMA
4 AIF User Non-secure DMA
5 TAC User Non-secure DMA
6 RAC User Non-secure DMA
7 FFTC User Non-secure DMA
8 QM_SS Second User Non-secure DMA
9 SRIO Packet
DMA/SRIO_M User/driven by SRIO block, user mode and supervisor mode is determined
by per transaction basis. Only the transaction with source ID matching the
value in SupervisorID register is granted supervisor mode. Non-secure DMA
10 QM_SS Packet
DMA/NETCP Packet DMA User Non-secure DMA
11 PCIe Supervisor Non-secure DMA
12 DebugSS Driven by Debug_SS Driven by
debug_SS DMA
13 HyperLink Supervisor Non-secure DMA
14 HyperLink Supervisor Non-secure DMA
15 TE_SCR_3M User Non-secure DMA
End of Table 7-51
Table 7-52 MPU0 Registers (Part 1 of 3)
Offset Name Description
0h REVID Revision ID
4h CONFIG Configuration
10h IRAWSTAT Interrupt raw status/set
14h IENSTAT Interrupt enable status/clear
18h IENSET Interrupt enable
1Ch IENCLR Interrupt enable clear
20h EOI End of interrupt
200h PROG0_MPSAR Programmable range 0, start address
204h PROG0_MPEAR Programmable range 0, end address
208h PROG0_MPPA Programmable range 0, memory page protection attributes
210h PROG1_MPSAR Programmable range 1, start address
214h PROG1_MPEAR Programmable range 1, end address