Texas Instruments TMS320C6670, Data Manual

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142 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
www.ti.com
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7.6 DDR3 PLL
The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset,
DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.
DDR3 PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit must
be added to all PLL supplies. See the
Hardware Design Guide for KeyStone Devices in 2.9 ‘‘Related Documentation
from Texas Instruments’’ on page 66 for detailed recommendations. For the best performance, TI recommends that
all the PLL external components be on a single side of the board without jumpers, switches, or components other
than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL
external components (C1, C2, and the EMI Filter).
Figure 7-21 DDR3 PLL Block Diagram
7.6.1 DDR3 PLL Control Registers
The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can
be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. This MMR
(memory-mapped register) exists inside the Bootcfg space. To write to these registers, software should go through
an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.4.3
‘‘PLL Settings’’
on page 35. See 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 73 for the address location of the
registers and locking and unlocking sequences for accessing the registers. These registers are reset on POR only.
.
Figure 7-22 DDR3 PLL Control Register (DDR3PLLCTL0)
(1)
1 This register is Reset on POR only
31 24 23 22 19 18 6 5 0
BWADJ[7:0] BYPASS Reserved PLLM PLLD
RW,+0000 1001 RW,+0 RW,+0001 RW,+0000000010011 RW,+000000
Legend: RW = Read/Write; - n = value after reset
DDR3
PH Y
DDRCLK ( N|P )
1
0
/2 xPLLM PLLD
BYPASS
/2
PLLOUT
DDR3 PLL