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TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
7.4.3 Soft Reset
A soft reset will behave like a hard reset except that the PCIe MMRs (memory-mapped registers)
and DDR3 EMIF
MMRs contents are retained. POR should also remain de-asserted during this time.
Soft reset is initiated by the following
•
RESET pin
•
RSCTRL Register in PLLCTL
•
Watchdog timer
All the above initiators by default are configured to act as hard reset. Except emulation, all of the other 3 initiators
can be configured as soft resets in the RSCFG register in PLLCTL.
In the case of a soft reset, the clock logic or the power control logic of the peripherals is not affected, and, therefore,
the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers
are
not
reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in
self-refresh mode before invoking the soft reset.
During a soft reset, the following happens:
1.
The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate
through the system. Internal system clocks are not affected. PLLs also remain locked.
2.
After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL
Controllers pause their system clocks for about 8 cycles.
At this point:
›
The state of the peripherals before the soft reset is not changed.
›
The I/O pins are controlled as dictated by the DEVSTAT register.
›
The DDR3 MMRs and PCIe MMRs retain their previous values. Only the DDR3 memory controller
and PCIe state machines are reset by the soft reset.
›
The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Because the configuration pins are not latched with
a system reset, the previous values, as shown in the DEVSTAT Register, are used to select the boot mode.
7.4.4 Local Reset
The local reset can be used to reset a particular CorePac without resetting any other device components.
Local reset is initiated by the following (for more details see the
Phase Locked Loop (PLL) Controller for KeyStone
Devices User Guide
2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66
):
•
LRESET pin
•
Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG
registers in the PLL Controller. See
‘‘Reset Configuration Register (RSTCFG)’’
on page 136 and
–
Local reset
–
NMI
–
NMI followed by a time delay and then a local reset for the CorePac selected
–
Hard reset by requesting reset via PLLCTL
•
LPSC MMRs (memory-mapped registers)
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