Texas Instruments TMS320C6670, Data Manual

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Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications 143
SPRS689D—March 2012
TMS320C6670
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7.6.2 DDR3 PLL Device-Specific Information
As shown in Figure 7-21 , the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory
controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3
PLL are affected as described in Section 7.4
‘‘Reset Controller’’ on page 122. DDR3 PLL is unlocked only during the
power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the
other resets.
7.6.3 DDR3 PLL Initialization Sequence
The Main PLL and PLL Controller must always be initialized prior to initializing the DDR3 PLL. The sequence
shown below must be followed to initialize the DDR3 PLL.
1. In DDR3PLLCTL1, write ENSAT = 1 (for optimal PLL operation)
2. In DDR3PLLCTL0, write BYPASS = 1 (set the PLL in Bypass)
3. In DDR3PLLCTL1, write PLLRST = 1 (PLL is reset)
4. Program PLLM and PLLD in DDR3PLLCTL0 register
Table 7-27 DDR3 PLL Control Register 0 Field Descriptions
Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
23 BYPASS Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
22-19 Reserved Reserved
18-6 PLLM A 13-bit field that selects the values for the multiplication factor
5-0 PLLD A 6-bit field that selects the values for the reference divider
End of Table 7-27
Figure 7-23 DDR3 PLL Control Register 1 (DDR3PLLCTL1)
31 14 13 12 7 6 5 4 3 0
Reserved PLLRST Reserved ENSAT Reserved BWADJ[11:8]
RW-000000000000000000 RW-0 RW-000000 RW-0 R-0 RW-0000
Legend: RW = Read/Write; - n = value after reset
Table 7-28 DDR3 PLL Control Register 1 Field Descriptions (DDR3PLLCTL1)
Bit Field Description
31-14 Reserved Reserved
13 PLLRST PLL reset bit.
0 = PLL reset is released.
1 = PLL reset is asserted.
12-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper operation of PLL
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
End of Table 7-28