Texas Instruments TMS320C6670, Data Manual

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68 Device Configuration Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
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3.2 Peripheral Selection After Device Reset
Several of the peripherals on the TMS320C6670 are controlled by the Power Sleep Controller (PSC). By default, the
PCIe, SRIO, HyperLink, RAC, TAC, FFTC, AIF2, TCP3d, TCP3e, and VCP are held in reset and clock-gated. The
memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on.
Then, the software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the
Power Sleep Controller (PSC) for KeyStone Devices User Guide in 2.9 ‘‘Related
Documentation from Texas Instruments’’ on page 66 .
3.3 Device State Control Registers
The TMS320C6670 device has a set of registers that are used to control the status of its peripherals. These registers
are shown in
Table 3-2 .
Table 3-2 Device State Control Registers (Part 1 of 4)
Address Start Address End Size Acronym Description
0x02620000 0x02620007 8B Reserved
0x02620008 0x02620017 16B Reserved
0x02620018 0x0262001B 4B JTAGID See section 3.3.3
0x0262001C 0x0262001F 4B Reserved
0x02620020 0x02620023 4B DEVSTAT See section 3.3.1
0x02620024 0x02620037 20B Reserved
0x02620038 0x0262003B 4B KICK0
See section 3.3.4
0x0262003C 0x0262003F 4B KICK1
0x02620040 0x02620043 4B DSP_BOOT_ADDR0 The boot address for C66x DSP CorePac0
0x02620044 0x02620047 4B DSP_BOOT_ADDR1 The boot address for C66x DSP CorePac1
0x02620048 0x0262004B 4B DSP_BOOT_ADDR2 The boot address for C66x DSP CorePac2
0x0262004C 0x0262004F 4B DSP_BOOT_ADDR3 The boot address for C66x DSP CorePac3
0x02620050 0x02620053 4B Reserved
0x02620054 0x02620057 4B Reserved
0x02620058 0x0262005B 4B Reserved
0x0262005C 0x0262005F 4B Reserved
0x02620060 0x026200DF 128B Reserved
0x026200E0 0x0262010F 48B Reserved
0x02620110 0x02620117 8B MACID See section 7.19 ‘‘Gigabit Ethernet (GbE) Switch Subsystem’’ on
page 207
0x02620118 0x0262012F 24B Reserved
0x02620130 0x02620133 4B LRSTNMIPINSTAT_CLR See section 3.3.6
0x02620134 0x02620137 4B RESET_STAT_CLR See section 3.3.8
0x02620138 0x0262013B 4B Reserved
0x0262013C 0x0262013F 4B BOOTCOMPLETE See section 3.3.9
0x02620140 0x02620143 4B Reserved
0x02620144 0x02620147 4B RESET_STAT See section 3.3.7
0x02620148 0x0262014B 4B LRSTNMIPINSTAT See section 3.3.5
0x0262014C 0x0262014F 4B DEVCFG See section 3.3.2