Texas Instruments TMS320C6670, Data Manual

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72 Device Configuration Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
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3.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets
and is locked after the first write. The Device Configuration Register is shown in
Figure 3-2 and described in
Table 3-4 .
Table 3-3 Device Status Register Field Descriptions
Bit Field Description
31-18 Reserved Reserved. Read only, writes have no effect.
17 PACLKSEL PA Clock select to select the reference clock for PA subsystem PLL
0 = Selects output of Main PLL MUX (SYSCLK vs. ALTCORECLK - depending on CORECLKSEL pin)
1 = Selects PASSCLKP/N
16 PCIESSEN PCIe module enable
0 = PCIe module disabled
1 = PCIe module enabled
15-14 PCIESSMODE[1:0] PCIe mode selection pins
00b = PCIe in end-point mode
01b = PCIe in legacy end-point mode (support for legacy INTx)
10b = PCIe in root complex mode
11b = Reserved
13-1 BOOTMODE[12:0] Determines the bootmode configured for the device. For more information on bootmode, see Section 2.4 ‘‘Boot Modes
Supported and PLL Settings’’ on page 30 and see the Bootloader for the C66x DSP User Guide in 2.9 ‘‘Related
Documentation from Texas Instruments’’ on page 66.
0 LENDIAN Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian mode or little
endian mode (default).
0 = System is operating in big endian mode
1 = System is operating in little endian mode (default)
End of Table 3-3
Figure 3-2 Device Configuration Register (DEVCFG)
31 1 0
Reserved SYSCLKOUTEN
R-0 R/W-1
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-4 Device Configuration Register Field Descriptions
Bit Field Description
31-1 Reserved Reserved. Read only, writes have no effect.
0 SYSCLKOUTEN SYSCLKOUT enable
0 = No clock output
1 = Clock output enabled (default)
End of Table 3-4