Texas Instruments TMS320C6670, Data Manual

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Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated Device Operating Conditions 105
SPRS689D—March 2012
TMS320C6670
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6 Device Operating Conditions
6.1 Absolute Maximum Ratings
Table 6-1 Absolute Maximum Ratings
(1)
Over Operating Case Temperature Range (Unless Otherwise Noted)
1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
Supply voltage range
(2)
:
2 All voltage values are with respect to V
SS
.
CVDD -0.3 V to 1.3 V
CVDD1 -0.3 V to 1.3 V
DVDD15 -0.3 V to 2.45 V
DVDD18 -0.3 V to 2.45 V
VREFSSTL 0.49 × DVDD15 to 0.51 × DVDD15
VDDT1, VDDT2, VDDT3 -0.3 V to 1.3 V
VDDR1, VDDR2, VDDR3
VDDR4, VDDR5, VDDR6
-0.3 V to 2.45 V
AVDDA1, AVDDA2, AVDDA3 -0.3 V to 2.45 V
VSS Ground 0 V
Input voltage (V
I
) range:
LVCMOS (1.8 V) -0.3 V to 0.3 V
DDR3 -0.3 V to 2.45 V
I
2
C -0.3 V to 2.45 V
LVDS -0.3 V to 0.3 V
LJCB -0.3 V to 1.3 V
SerDes -0.3 V to CVDD1+0.3 V
Output voltage (V
O
) range:
LVCMOS (1.8 V) -0.3 V to 0.3 V
DDR3 -0.3 V to 2.45 V
I
2
C -0.3 V to 2.45 V
SerDes -0.3 V to CVDD1+0.3 V
Operating case temperature range, T
C
:
Commercial 0°C to 100°C
Extended -40°C to 100°C
ESD stress voltage, V
ESD
(3)
3 Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
HBM (human body model)
(4)
4 Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD
control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.
±1000 V
CDM (charged device model)
(5)
5 Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control
process. Pins listed as 250 V may actually have higher performance.
±250 V
Overshoot/undershoot
(6)
6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8V LVCMOS signals is DVDD18 + 0.20
×
DVDD18 and
maximum undershoot value would be V
SS
- 0.20
×
DVDD18
LVCMOS (1.8 V)
20% overshoot/undershoot for 20% of
signal duty cycle
DDR3
I
2
C
Storage temperature range, T
stg
: -65°C to 150°C
End of Table 6-1