Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
205
SPRS689D—March 2012
TMS320C6670
7.15 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and a
UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550
asynchronous communications element, which, in turn, is a functional upgrade of the TL16C450. Functionally
similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate
FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per
byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial
conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes
control capability and a processor interrupt system that can be tailored to minimize software management of the
communications link. For more information on UART, see the
Universal Asynchronous Receiver/Transmitter
(UART) for KeyStone Devices User Guide
in
2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66
Figure 7-43
UART Receive Timing Waveform
Figure 7-44
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
Table 7-72
UART Timing Requirements
(see
and
No.
Min
Max
Unit
Receive Timing
4
tw(RXSTART)
Pulse width, receive start bit
0.96U
(1)
1 U = UART baud time = 1/programmed baud rate
1.05U
ns
5
tw(RXH)
Pulse width, receive data/parity bit high
0.96U
1.05U
ns
5
tw(RXL)
Pulse width, receive data/parity bit low
0.96U
1.05U
ns
6
tw(RXSTOP1)
Pulse width, receive stop bit 1
0.96U
1.05U
ns
6
tw(RXSTOP15)
Pulse width, receive stop bit 1.5
0.96U
1.05U
ns
6
tw(RXSTOP2)
Pulse width, receive stop bit 2
0.96U
1.05U
ns
Autoflow Timing Requirements
8
td(CTSL-TX)
Delay time, CTS asserted to START bit transmit
P
(2)
2 P = 1/SYSCLK7
5P
ns
End of Table 7-72
6
5
5
4
Stop/Idle
R
X
D
Start
Bit 0
Bit 1
Bit N-1
Bit N
Parit
y
Stop
Idle
Start
8
T
X
D
Bit N-1
Bit N
Stop
Start
Bit 0
CTS
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