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TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
7.8 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device CPU.
There are 3 EDMA channel controllers on the device: EDMA3CC0, EDMA3CC1, and EDMA3CC2.
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EDMA3CC0 has two transfer controllers: EDMA3TC1 andEDMA3TC2.
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EDMA3CC1 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.
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EDMA3CC2 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.
In the context of this document, EDMA3TCx is associated with EDMA3CCy, and is referred to as EDMA3CCy TCx.
Each of the transfer controllers has a direct connection to the switch fabric. Section
lists the peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR-3 subsytems. The others are
used for the remaining traffic.
Each EDMA3 channel controller includes the following features:
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Fully orthogonal transfer description
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3 transfer dimensions:
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Array (multiple bytes)
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Frame (multiple arrays)
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Block (multiple frames)
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Single event can trigger transfer of array, frame, or entire block
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Independent indexes on source and destination
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Flexible transfer definition:
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Increment or FIFO transfer addressing modes
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Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
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Chaining allows multiple transfers to execute with one event
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128 PaRAM entries for EDMA3CC0, 512 each for EDMA3CC1 and EDMA3CC2
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Used to define transfer context for channels
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Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
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16 DMA channels for EDMA3CC0, 64 each for EDMA3CC1 and EDMA3CC2
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Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
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8 Quick DMA (QDMA) channels per EDMA3CCx
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Used for software-driven transfers
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Triggered upon writing to a single PaRAM set entry
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Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0, four
transfer controllers and four event queues with programmable system-level priority for each of EDMA3CC1
and EDMA3CC2
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Interrupt generation for transfer completion and error conditions
Summary of Contents for TMS320C6670
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