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TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
SRIOSGMIICLK[P:N]
1
tc(SRIOSMGMIICLKN)
Cycle time SRIOSMGMIICLKN cycle time
3.2 or 4 or 6.4
ns
1
tc(SRIOSMGMIICLKP)
Cycle time SRIOSMGMIICLKP cycle time
3.2 or 4 or 6.4
ns
3
tw(SRIOSMGMIICLKN)
Pulse width SRIOSMGMIICLKN high
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKN)
Pulse width SRIOSMGMIICLKN low
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKP)
Pulse width SRIOSMGMIICLKP high
0.45*tc(SRIOSGMIICLKP)
0.55*tc(SRIOSGMIICLKP)
ns
3
tw(SRIOSMGMIICLKP)
Pulse width SRIOSMGMIICLKP low
0.45*tc(SRIOSGMIICLKP)
0.55*tc(SRIOSGMIICLKP)
ns
4
tr(SRIOSMGMIICLKN_250mv)
Transition time SRIOSMGMIICLKN rise time
(250 mV)
50
350
ps
4
tf(SRIOSMGMIICLKN_250mv)
Transition time SRIOSMGMIICLKN fall time
(250 mV)
50
350
ps
4
tr(SRIOSMGMIICLKP_250mv)
Transition time SRIOSMGMIICLKP rise time
(250 mV)
50
350
ps
4
tf(SRIOSMGMIICLKP_250mv)
Transition time SRIOSMGMIICLKP fall time
(250 mV)
50
350
ps
5
tj(SRIOSMGMIICLKN)
Jitter, RMS SRIOSMGMIICLKN
4 ps, RMS
5
tj(SRIOSMGMIICLKP)
Jitter, RMS SRIOSMGMIICLKP
4 ps, RMS
5
tj(SRIOSMGMIICLKN)
Jitter, RMS SRIOSMGMIICLKN (SRIO not used)
8 ps, RMS
5
tj(SRIOSMGMIICLKP)
Jitter, RMS SRIOSMGMIICLKP (SRIO not used)
8 ps, RMS
HyperLink CLK[P:N]
1
tc(MCMCLKN)
Cycle time MCMCLKN cycle time
3.2 or 4 or 6.4
ns
1
tc(MCMCLKP)
Cycle time MCMCLKP cycle time
3.2 or 4 or 6.4
ns
3
tw(MCMCLKN)
Pulse width MCMCLKN high
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
ns
2
tw(MCMCLKN)
Pulse width MCMCLKN low
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
ns
2
tw(MCMCLKP)
Pulse width MCMCLKP high
0.45*tc(MCMCLKP)
0.55*tc(MCMCLKP)
ns
3
tw(MCMCLKP)
Pulse width MCMCLKP low
0.45*tc(MCMCLKP)
0.55*tc(MCMCLKP)
ns
4
tr(MCMCLKN_250mv)
Transition time MCMCLKN rise time (250 mV)
50
350
ps
4
tf(MCMCLKN_250mv)
Transition time MCMCLKN fall time (250 mV)
50
350
ps
4
tr(MCMCLKP_250mv)
Transition time MCMCLKP rise time (250 mV)
50
350
ps
4
tf(MCMCLKP_250mv)
Transition time MCMCLKP fall time (250 mV)
50
350
ps
5
tj(MCMCLKN)
Jitter, RMS MCMCLKN
4 ps, RMS
5
tj(MCMCLKP)
Jitter, RMS MCMCLKP
4 ps, RMS
PCIECLK[P:N]
1
tc(PCIECLKN)
Cycle time PCIECLKN cycle time
3.2 or 4 or 6.4 or 10
ns
1
tc(PCIECLKP)
Cycle time PCIECLKP cycle time
3.2 or 4 or 6.4 or 10
ns
3
tw(PCIECLKN)
Pulse width PCIECLKN high
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2
tw(PCIECLKN)
Pulse width PCIECLKN low
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2
tw(PCIECLKP)
Pulse width PCIECLKP high
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
3
tw(PCIECLKP)
Pulse width PCIECLKP low
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
4
tr(PCIECLKN_250mv)
Transition time PCIECLKN rise time (250 mV)
50
350
ps
4
tf(PCIECLKN_250mv)
Transition time PCIECLKN fall time (250 mV)
50
350
ps
4
tr(PCIECLKP_250mv)
Transition time PCIECLKP rise time (250 mV)
50
350
ps
4
tf(PCIECLKP_250mv)
Transition time PCIECLKP fall time (250 mV)
50
350
ps
Table 7-26
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
(1)
(see
Figure 7-19
and
Figure 7-20
)
No.
Min
Max
Unit
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