Texas Instruments TMS320C6670, Data Manual

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132 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
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7.5.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 7-8 and
described in Table 7-15 .
0231 0174 - 0231 0193 PLLDIV9 - PLLDIV16 Reserved
0231 0194 - 0231 01FF - Reserved
End of Table 7-14
Figure 7-8 PLL Secondary Control Register (SECCTL))
31 24 23 22 19 18 0
Reserved BYPASS OUTPUT DIVIDE Reserved
R-0000 0000 RW-1 RW-0001 RW-001 0000 0000 0000 0000
Legend: R/W = Read/Write; R = Read only; - n = value after reset
Table 7-15 PLL Secondary Control Register Field Descriptions
Bit Field Description
31-24 Reserved Reserved
23 BYPASS Main PLL bypass enable
0 = Main PLL bypass disabled
1 = Main PLL bypass enabled
22-19 OUTPUT DIVIDE Output divider ratio bits
0h = ÷1. Divide frequency by 1
1h = ÷2. Divide frequency by 2
2h - Fh = Reserved
18-0 Reserved Reserved
End of Table 7-15
Table 7-14 PLL Controller Registers (Including Reset Controller) (Part 2 of 2)
Hex Address Range Acronym Register Name