Texas Instruments TMS320C6670, Data Manual

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146 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
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7.7.2 PASS PLL Device-Specific Information
As shown in Figure 7-25 , the output of PASS PLL (PLLOUT) is divided by 3 and directly fed to the Network
Coprocessor. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks of the PASS
PLL are affected as described in Section 7.4
‘‘Reset Controller’’ on page 122. The PASS PLL is unlocked only during
the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of
the other resets.
7.7.3 PASS PLL Initialization Sequence
The Main PLL and PLL Controller must always be initialized prior to initializing the PASS PLL. The sequence shown
below must be followed to initialize the PASS PLL.
1. In PASSPLLCTL1, write ENSAT = 1 (for optimal PLL operation)
2. In PASSPLLCTL0, write BYPASS = 1 (set the PLL in Bypass)
Table 7-30 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
23 BYPASS Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
22-19 Reserved Reserved
18-6 PLLM A 13-bit field that selects the values for the multiplication factor (see note below)
5-0 PLLD A 6-bit field that selects the values for the reference divider
End of Table 7-30
Figure 7-27 PASS PLL Control Register 1 (PASSPLLCTL1)
31 15 14 13 12 7 6 5 4 3 0
Reserved PLLRST PLLSELECT Reserved ENSAT Reserved BWADJ[11:8]
RW-00000000000000000 RW-0 0 RW-0000000 RW-0 R-0 RW-0000
Legend: RW = Read/Write; - n = value after reset
Table 7-31 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
Bit Field Description
31-15 Reserved Reserved
14 PLLRST PLL reset bit
0 = PLL reset is released.
1 = PLL reset is asserted.
13 PLLSELECT PASS PLL Select Bit
0 - Reserved
1 - PASS PLL output clock is used as the input to PASS
12-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper operation of PLL
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
End of Table 7-31