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TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
7.4 Reset Controller
The reset controller detects the different type of resets supported on the TMS320C6670 device and manages the
distribution of those resets throughout the device.
The device has the following types of resets:
•
Power-on reset
•
Hard reset
•
Soft reset
•
Local reset
explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section 7.4.7
7.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following
1.
POR pin
2.
RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal
operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device, including the
reset-isolated logic, when the device is already powered up. For this reason, the RESETFULL pin, unlike POR, should
be driven by the on-board host control other than the power good circuitry. For power-on reset, the Main PLL
Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or
the dividers in the PLL Controller.
Table 7-9
Reset Types
Type
Initiator
Effect(s)
Power-on Reset
POR pin
RESETFULL pin
Resets the entire chip including the test and emulation logic. The device configuration pins are
latched only during power-on reset.
Hard Reset
RESET pin
PLLCTL
(1)
register (RSCTRL)
Watchdog timers
Emulation
1 All masters in the device have access to the PLLCTL registers.
Hard reset resets everything except for test, emulation logic and reset isolation modules. This reset
is also different from power-on reset in that the PLLCTL assumes power and clocks are stable when
hard reset is asserted. The device configurations pins are not re-latched.
Emulation initiated reset is always a hard reset.
By default these initiators are configured as Hard reset, but can be configured (Except Emulation)
as soft reset in the RSCFG register of PLLCTL. Contents of DDR3 SDRAM memory can be retained
during a hard reset if the SDRAM is placed in self-refresh mode.
Soft Reset
RESET pin
PLLCTL register (RSCTRL)
Watchdog timers
Soft Reset will behave like hard reset except that PCIe MMRs (memory-mapped registers) and
DDR3 EMIF MMRs contents are retained.
By default these initiators are configured as hard reset, but can be configured as Soft reset in the
RSCFG register of PLLCTL. Contents of DDR3 SDRAM memory can be retained during a soft reset if
the SDRAM is placed in self-refresh mode.
Local Reset
LRESET pin
Watchdog timer timeout
LPSC MMRs
Resets the CorePac, without disturbing clock alignment or memory contents. The device
configuration pins are not re-latched.
End of Table 7-9
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