Teledyne ULTRAFLOW 150, Operation Manual, Page: 29 / 162

SECTION 5.0, TRANSDUCER INTERFACE ENCLOSURE
Figure 5-3A Figure 5-3B
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Note: The scales of the “X” axes are not the same.
5.2.3.3 Receive Signal Select, Gain, Digitization, Integration and Storage
When the FPGA determines it is time to read the receive signal from a particular
transducer/preamp it sends the appropriate channel select code to the four channel
multiplexer. The multiplexer then places the desired analog receive signal on the
input of the “A” half of a dual DAC. The DAC applies the appropriate gain that
is determined by the FPGA to this signal and places the result on the input of a
twelve bit Analog to Digital converter (ADC). The ADC begins doing a
conversion when it receives a start signal from the FPGA. Each conversion takes
0.5
µsec. At the end of each conversion the digital value is passed to the FPGA
where it is filtered, rectified, and added to the appropriate boxcar in the RAM.
Another start signal is then issued and the ADC starts another conversion cycle.
This continues for 32,384 cycles creating a sixteen millisecond wide window of
0.5
µ
sec filtered digital averages. The RAM has a separate boxcar window for
each transducer. After the digitized window is complete the FPGA channel select
requests a different transducer/preamp signal from the multiplexer and the ADC
conversions begin forming the digital, (boxcar) window for that transducer. The
channel select continues cycling through the transducers and adding conversions
to the boxcars in the window until the desired integration time is over. This is
typically 30 seconds. At the end of the integration period the FPGA sends a
“Measurement Complete” signal to the 332 Processor. The 332 Board issues a
“Wait” signal to the FPGA, while it reads the four windows of “Boxcar” data, and
processes the data into time measurements and velocity readings. Then it begins
the next sampling cycle for the duration of the integration period.
E S Transducer Drive (50 KHZ) LR003 Transducer Drive (20
5-5