Teledyne ULTRAFLOW 150, Operation Manual, Page: 27 / 162

SECTION 5.0, TRANSDUCER INTERFACE ENCLOSURE
150BlockDiagram.ppt
21 Feb. 2001
ELM
FPGA
4
Channel
Mux
12 bit
Parallel
2MSPS
ADC
ADS803
12 MHz
Oscillator
Dual 8 Bit
Parallel
Multiplying
DAC
TLC7528
From Preamp
Purge Switch
Circuits
From Preamp
Analog
Output
Circuits
To
Preamp
Transmit
Drive
Input
Circuits
To Preamp
AGC DAC’s
(1 per
Preamp)
Start Start ADC
Gain Bus &
Waveform
Data
(8 Data & 3
Control
Lines)
Channel
Selects
SPI Clock, Input and Output Data Lines, 4 SPI Slave Selects
Wait / Measure*
Serial
Configuration
Inputs
Measurement Complete
Config
Device
3.3V Bus
Xcvr’s
D0 to D15, R/W
A0 to A18,
CS6,7,9,10
IRQ5
TPU
I/O
TPU I/O
SBC332 Board
ADC
Data
Input
D0 to D15,
A0 to A18,
CS6,7,9,10,
R/W
NEURON
Circuit
FTT10A
Network Wires
Bus Xcvr
Renew*
Real Time
Clock
DB
Connector
DB
Connector
To 6 Point
I/O
To Display
Control
128Kx8
SRAM
Buffer
&
ESD
Network
SPI
Clock
& Data
Slave
Selects
12 Bit
Parallel
DAC312
Test Point
(like TP4)
Diagnostic Output
12 lines
RESET Sync
A out
B out
To Channel Selects
128Kx8
SRAM
128Kx8
SRAM
TPU
I/O
1 of 4
Transmit Select
Binary Coded
Receive Select
Mode_1
Mode_2
CONFIG_DONE
Boxcar Overflow
DIAG_0
DIAG_1
JUx Logic 0 or 1
JUy Logic 0 or 1
INIT_DONE
3.3V
Bus
Xcvr’s
4 to 16
Decoder
Over-range OVR
Boxcar RAM Busy
RECONFIG
+3.3V
RS232
Port
DB
Connector
Figure 5-2
Flow Mother Board Block Diagram
5-3