Tektronix 2445, Instruction Manual

Page: 61 / 351

Theory of Operation—2445 Service
used to set the charging current fo r holdoff-ramp inte­
grating capacitor C660. A control voltage from digital-to-
analog converter (DAC) U2234 (diagram 2) via multiplexer
U170 (diagram 4) is stored on C l 80. The stored voltage
level sets the base voltage for both Q154 and Q155 via
amplifier U165C. Transistors Q154 and Q155 form a
current-mirror w ith
nearly equal collector currents.
Transistor Q154 is a current-to-voltage converter that
provides negative feedback to U165C, setting loop gain.
Transistor Q155 acts as a constantcurrent source that
charges integrating capacitor C660, producing a linear
holdoff ramp.
A comparator circuit in U650 detects when the ramp
crosses a predefined threshold voltage (approximately
+3 V). When the threshold is reached, pin 10 of U650
(HRR) goes LO and the integrating capacitor is discharged.
A t that same time, an internal counter that keeps track
of the holdoff ramp cycles is incremented. The ramps
continue to be generated and reset until the holdoff ramp
counter has counted the number o f ramp cycles defined
by the sweep-rate-dependent holdoff data field stored in
the Display Sequencer control register. A t all sweep speeds
except 5 ns per division, the count is at least two holdoff
ramp cycles. The front-panel variable HOLDOFF control
affects holdoff time by varying the HOLDOFF control
voltage to U165C (from the DAC), changing the charging
rate of integrating capacitor C660.
When holdoff time requirements are met (determined
by the number of ramps counted), the Display Sequencer
sets the THO (trigger holdoff) signal LO. This enables both
the A Sweep hybrid (U700) and the A Trigger circuitry
in U500. The Trigger circuit begins monitoring the selected
trigger source line and, when a triggering event is detected
that meets the triggering requirements defined by the
stored control data, initiates the A Sweep and sets the TSA
(trigger status, A Sweep) line to Display Sequencer U650
LO (indicating that the A Sweep has been triggered).
As the A Sweep circuit (U700) responds to the trigger,
it sets the SGA (sweep gate A) line LO (via U980A)
indicating that an A Sweep is in progress. A fter the sweep
has run to completion, U700 sets the SGA line HI signaling
the end of sweep. The Display Sequencer then sets the THO
iine Hi, resetting the A/B Trigger hybrid U500 and A
Sweep hybrid U700 in preparation fo r the next sweep.
D ELAY GATE OPERATION. Analog Switches U850B
and U850C select the delay references for each sweep.
Depending on the display mode and point in the display
sequence, the DS control signal (U650 pin 40) routes one
of the tw o analog delay references through U850B and
U850C to the tw o sweep hybrids. The selected reference
level is compared against the changing sweep ramp voltages
to generate the delay gates that control each sweep's
functions.
A fter an A Sweep has been initiated by a trigger, a delay
gate circuit w ithin U700 compares the A Sweep ramp
voltage to the selected delay reference. When the sweep
ramp reaches the delay reference level, the DG (delay gate)
output goes LO, enabling the B trigger portion o f U500 and
B Sweep hybrid U900. Then, when B triggering occurs (for
TRIG AFT DLY mode), the A/B Trigger hybrid sets the
TGB (trigger gate B) signal LO, initiating the B Sweep. In
RUN A F T DLY mode, however, the TGB signal to U900 is
held LO, and the B Sweep is initiated at the end of the A
Sweep delay time when the A Sweep delay gate goes LO.
STATUS MONITORING. As the Display Sequencer
controls the display system in real time, it continually
monitors the trigger and sweep operations and updates the
internal trigger status register accordingly. The Micro­
processor checks the contents of this register every 3.3 ms
to determine the current status of the trigger and sweep
circuitry. The Microprocessor reads the trigger status
register by generating a series o f trigger status strobe (TSS)
pulses (U650 pin 19) to serially clock the contents of the
register out to the TSO (trigger status output) line and onto
the Data Bus (via Status Buffer U2108 on diagram 2). The
system status information obtained by this check is used
fo r AUTO LV L triggering, AUTO free-run triggering,
detecting the completion of all the sweeps in a SGL SEQ
display, and during instrument calibration.
INTENSITY CONTROL. The Display Sequencer con­
trols the intensity fo r both sweep and readout displays.
The analog levels at pins 22 and 23 (set by the front-panel
INTENSITY and READOUT INTENSITY controls) deter­
mine the basic intensity level of the displays. Two inter­
nally generated DAC currents (developed by m ultiplying
the I REF current at pin 20 by two processor-generated
numbers stored internally) are added to the basic intensity
level currents to produce the display intensity seen on the
crt (see Table 3-1). The tw o DAC currents added to the
INTENSITY current are dependent on sweep speed, num­
ber o f channels being displayed, and whether or not the
X I 0 MAG feature is in use. These added currents increase
crt beam current and hold the display intensity some­
what constant under the varying display conditions. The
resulting current is applied to Z-Axis A m plifier U950
(diagram 6) from the BRIGHT output o f the Display
Sequencer (pin 21).
To produce the intensified zone on the A Sweep trace
fo r A intensified by B Sweep displays, an additional current
is added to the c rt drive signal by the Z-Axis Am plifier
during the concurrence of the SGAZ and SGBZ (sweep gate
A and B z-axis) signals.
3-19