Tektronix 2445, Instruction Manual

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Theory o f Operation—2445 Service
signal that a new dot display is allowed. The HI from
U2970C enables most o f the gating in the Dot Start
Governor. If the Refresh Prioritizer has encoded a display
p rio rity of either one or two, the output o f exclusive-OR-
gate U2990B is HI. When DOTOK from U2970C goes HI
to enable a dot display, the LO reset from pin 6 o f U2970B
to pin 1 o f flip-flop U2880A is removed. Now, when the
A Sweep gate (SGA) goes HI (beginning o f Holdoff), the
HI at the_D input of U2880A is clocked to the Q output
and the Q o utput at pin 6 w ill go LO, requesting display of
a p rio rity one or tw o dot. This LO dot request is propa­
gated through U2885B, U2890D, U2890B, and U2890C
and sets the STARTDOT signal LO. STARTDOT going
LO resets Dot Cycle Generator shift register U2995 and
counter U2830B o f the Dot Timer. Resetting the Dot Cycle
Generator shift register causes the REST signal from
U2995 pin 13 to go to a LO, removing the HI DOTOK
signal at U2970C pin 8. As DOTOK goes LO, STARTDOT
at pin 8 of U2890C goes HI to start the Dot Cycle Gener­
ator. A t the same time the reset to U2880A is asserted via
U2970B and the dot request is removed. Both the Dot
Timer and the Dot Cycle Generator are now enabled and
start the firs t dot-display cycle during holdoff time.
A fte r the Display Sequencer U650 (diagram 5) has time
to respond to the end of the sweep gate, it sets the readout
active signal (ROA) to pin 4 of U2880A LO. This sets pin 5
of U2855B LO, and the signal is propagated through
U2855B, U2890D, U2890B, and U2890C, as before, reset­
ting the Dot Timer and the Dot Cycle Generator. REST
then goes LO as before and starts the Dot Cycle Generator
and Dot Timer. This cycle continues, displaying one dot per
cycle (except for the first nondisplayed dot o f a character
which is automatically initiated by EOCH2), until the
Display Sequencer determines that the readout time is over
(sets ROA HI) or until the display priority is decremented
to zero.
When a display p riority of three or four exists, the out­
put o f U2990B w ill be LO, and U2970B, U2880A, and the
associated logic gates following it w ill not be able to initiate
a dot cycle. In either of these display priorities, U2970D,
U2835C, U2980A, U2965B, and flip-flop U2950B detect
the higher p riority and generate a readout request signal
(ROR) to the Display Sequencer. The LO from U2950B
pin 8 propagates through U2890B and U2890C to initiate a
STARTDOT cycle. When the Display Sequencer recognizes
that the readout request signal is LO, it w ill perform the
mode-dependent setup functions necessary to give display
control to the Readout Board and w ill then set the ROA
(readout active) line LO. The LO w ill be clocked into
U2880B, and the Dot Cycle Generator w ill generate a
GETDOT signal, resetting the readout request from flip-
flo p U2950B. Only one dot is displayed fo r each readout
request.
A similar readout display request w ill be generated when
priority-two-or-higher displays are required when sweep
gates are not present (dot display during triggerable time
after holdoff). This condition is detected by NAND-gate
U2885A. AND-gate U2970D allows a readout request to be
generated when in the interfere mode. This mode is invoked
only during a single-sequence waveform display and ensures
that all of the selected sweep combinations are displayed
once, followed by a complete readout frame (for the
purpose of crt photography).
Dot Cycle Generator
The Dot Cycle Generator, composed of shift register
U2995, flip-flop U2880B, and associated gating circuitry,
generates time-related signals for the following purposes:
unblanking the crt to display a dot; requesting the next
byte of dot data in preparation fo r displaying the next
dot; and reenabling itself to repeat the tasks, via the Dot
Start Governor (dependent on the display priority).
The timing relationships of the Dot Cycle Generator
output signals are controlled by shift register U2995.
When the Dot Start Governor initiates a STARTDOT
cycle as previously described, the STARTDOT signal
initially goes LO, resetting all the Q outputs of U2995
LO and setting the Q output of flip-flop U2880B to a HI.
The STARTDOT signal is then returned HI, and Dot Timer
counter U2830A and shift register U2995 are enabled. The
shift register begins to consecutively shift HI logic levels to
its Q output pins w ith each 5-MHz clock from Dot Timer.
A fter approximately 400 ns, pin 5 (Qc ) o f the shift register
w ill go HI. The HI at Qc propagates through exclusive-OR-
gate U2990D and AND-gate U2970A to unblank the crt by
setting the readout blanking signal (ROB) HI.
When the QF output of U2995 goes HI (1 jus after
STARTDOT), the output o f U2990D goes LO and the out­
put o f U2990C goes HI. The LO from U2990D propagates
through U2970A to blank the crt (ROB goes LO) and to
clock flip-flop U2880B via inverter U2890C. The ROA
(readout active) level from the Display Sequencer (dia­
gram 5) is clocked from the D input (pin 12) o f U2880B to
the Q output; and, if LO (indicating that the readout
circuitry had control o f the crt when unblanking occurred;
thus the dot was displayed), the output o f U2980B is set
HI. With three HI levels applied to NAND-gate U2885C, a
GETDOT request is generated to get the next byte of
dot-position data fo r display. The next 5-MHz clock sets
the Q
q
output o f U2995 HI, and the output of U2990C
goes LO. removing the LO GETDOT signal.
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