Tektronix 2445, Instruction Manual

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Theory o f Operation—2445 Service
* N 0 T E : I F S0 IS ALSO HI AT T H I S TIME > THE PRIO RIT Y DOES NOT CHANGE.
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Figure 3-9. Timing of Refresh Prioritizer.
If a second ROSFRAME request occurs before the
Character Counter indicates the end o f the subframe (to
decrement the prioritizer back to zero), input SI o f U2985
w ill be set HI (while the SO input pin remains LO) and the
Prioritizer w ill increment to p riority tw o (outputs Qc
and Q
d
go HI) on the next STARTDOT cycle. If this
display p riority still is inadequate to complete the subframe
display before the next ROSFRAME request occurs, prior­
ity two w ill be incremented up to priority three, or even to
priority four should the condition persist. Priority four is
operationally the same as priority three, but it is used to
keep the readout circuitry continuously displaying readout
data on through the next subframe, thus allowing the
display to catch up. If p riority four is in effect, the next
decrement that occurs at the end o f a subframe only
returns the prioritizer to p riority three, not to priority two.
The circuit composed o f flip-flop U2950A and exclusive-
OR-gate U2990A enables either edge o f the CA3 b it to
decrement the p riority of the display when a subframe
is completed. Either a negative or positive transition on
pin 2 of U2990A w ill cause the output at pin 3 to go HI
since the Q output of U2950A is still at the opposite level.
The HI from U2990A indicates that the end of the present
subframe has occurred, and it sets up the prioritizer to
decrement w ith the next REFRESH clock. A t the same
time that the prioritizer decrements, the changed level of
the CA3 bit is clocked through U2950A and causes the
output of exclusive-OR-gate U2990A to return LO until
the next subframe is completed.
If the subframe is completed (SO on U2985 goes HI)
when a ROSFRAME request is also pending (SI is also HI),
U2985 does a parallel load, reloading the present p riority
back into the prioritizer. Since, in this case, the subframe
display was completed at the same rate as the ROSFRAME
request occurred, the readout display priority is not
changed.
Dot Start Governor
The Dot Start Governor detects the display priority
from the Refresh Prioritizer and initiates doi-dispiay cycles
as the appropriate conditions are met. The conditions
tested include display p riority, sweep gate completion, dot
completion, readout control status, and the readout active
enable from the Display Sequencer.
When the readout board status line (ACTIVE/
ADDRESSABLE) is HI (signifying display) and the REST
line goes HI to indicate that the dot cycle is complete,
AND-gate U2970C generates a HI at pin 8 (DOTOK) to
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