Tektronix 2445, Instruction Manual

Page: 49 / 351

Theory of Operation—2445 Service
is suspected o f causing a system failure) or fo r trouble­
shooting the Address Bus and Address Decode circuitry.
Removing the jumper removes the operating power from
both U2194 and U2294 to disconnect the Microprocessor
from the buffered Data Bus. With the Data Bus discon­
nected, a resistor network pulls the processor Data Bus lines
(DO through D7) to a NOP (no operation) instruction. A
NOP causes the Microprocessor to continuously increment
through its address field. The Address Decode circuitry may
then be checked to determine if it is operating properly.
Address Decode
The Address Decode circuitry generates enabling signals
and strobes that allow the Microprocessor to control the
various devices and circuit functions. The controlling signals
are generated as a result of the Microprocessor placing
specific addresses on the Address Bus. Figure 3-2 illustrates
the enables and strobes generated by the Address Decode
circuitry.
Address decoding is performed by a series o f three-line-
to-eight-line decoders attached to the Address Bus. The
three most significant address bits are decoded by U2480.
This device initially separates the total addressable-memory
space (64k-bytes) into eight, 8k-byte blocks. Addresses in
the top 32k-bytes (address b it A15 Hi) select one of four
read-only memories (ROM), U2162, U2178, U2362, or
U2378. When the VM A (Valid Memory Address) and E
(Enable) outputs from the Microprocessor go HI, the
HEX DECODED BY
ADDRESS U 2 480 AND U 2770
HEX DECODED BY
ADDRESS U 2580
HEX
ADDRESS
0000
07FF
0 8 0 0
0FFF
1000
7FFF
8 0 0 0
9FFF
A000
BFFF
C000
DFFF
E000
FFFF
RAM-U2496
ADDRESS
DECODING (U 2 5 8 0 )
RESERVED
FOR OPTIONS
R 0M -U2162
R 0M -U2362
R0M -U 2378
R0M -U 2178
0 8 0 0
0 8 3 F
0 8 4 0
0 87F
0 8 8 0
\ 08BF
\ 08C0
08FF
, 0 9 0 0
' 0 93F
\ 0 9 4 0
\ 097F
\ 0 9 8 0
09BF
' 09C0
\ 09FF
\ 0A00
\ 0BFF
> 0C00
0DFF
' 0E00
\ 0FFF
UNUSED
DAC MSB CLK (0 8 7 F )
1 09C0
/ ---------
/ 09C1
DAC LSB CLK ( 0 8 8 0 )
PORT 1 CLK (0 8 C 0 )
/
/
/
/
ROS 1 CLK ( 0 9 0 0 ) /
ROS 2 CLK ( 0 9 4 0 )
PORT 2 CLK ( 0 9 8 0 )
FURTHER ADDRESS
DECODING ( U 2 5 9 6 )
OVERLAY OF
0 8 0 0 -0 9 F F
OVERLAY OF
0 8 0 0 -0 9 F F
OVERLAY OF
0 8 0 0 -0 9 F F
/
/
/
J
\
\
\
\
\
\
09C2
09C3
09C4
09C5
09C6
09C7
09C8
09C9
09CA
09CB
09CC
\ 09CD
\ -------------
> 09CE
09CF
' 09D0
' 09DF
\ 09E 0
\ 09EF
> 0 9 F 0
09FF
DECODED BY
U 2 596
UNUSED
DMUX0 OFF
DMUX0 ON
PORT 3 IN
DMUX1 OFF
DMUX1 ON
LED CLK
D IS P . SEQ. CLK
ATTN. CLK
CH 2 PA CLK
CH 1 PA CLK
B SWP CLK
A SWP CLK
B TRIG CLK
A TRIG CLK
TRIG STAT STRB
OVERLAY OF 0 9 C 0 -0 9 C F
OVERLAY OF 0 9 C 0 -0 9 C F
OVERLAY OF 0 9 C 0 -0 9 C F
3831-09
3-7
Figure 3-2. Address decoding.