Tektronix 2445, Instruction Manual

Page: 71 / 351

Theory o f Operation—2445 Service
The character data register U2860 also provides a means
for the Microprocessor to read data from the Character
RAM fo r partial verification of Readout circuit operation
(during the power-up tests). The eight bits of parallel data
from the Character RAM location selected by character
address register U2960 are loaded into U2860 by setting
b it Q3 o f mode control register U2865 LO. Inverter
U2965C converts the LO to a HI and applies it to character
register U2860 at pin 1. The HI on pin 1, in combination
w ith the fixed HI on pin 19 of U2860, switches the char­
acter register to the Load mode. The next positive tran­
sition o f the ROS1 strobe loads the eight data bits placed
on the CDO through CD7 bus lines into the register in
parallel. Bit Q3 is then returned HI, and the next positive
transition of the ROS1 strobe shifts the QA b it to pin 8
(Qa '), the RO DO (readout data out) line. Seven more
ROS1 strobes shift the remaining seven bits of character
data out onto the RO DO line to Status Buffer U2108
(diagram 2) to be read, one at a time, by the processor.
Character RAM
Character RAM U2920 provides temporary storage of
the readout character selection data. This character data is
organized as 128 eight-bit words that define the character
that should be displayed at any given readout position on
the crt. Cursor information is aiso stored in U2920 when
cursors are to be displayed.
RAM locations may be addressed either from the Read­
out I/O stage by character address register U2960, as
previously described, or by the Character Counter stage.
The lower 64 address locations in RAM each correspond to
a specific readout location on the crt, while the upper 64
address locations store cursor information. The eight bits of
data written to one of these locations from the Readout
I/O stage is a code that identifies the specific character (or
cursor segment) that should be displayed at the associated
crt location. A fter the display data is w ritten into the RAM,
the Character Counter is allowed to address the RAM,
incrementing through the RAM address field. The eight-bit
character codes for each display location are output to
Character ROM U2930 in sequence.
Character Counter
The Character Counter stage consists of two four-bit
counters (U2940A and B) cascaded together to form an
eight-bit counter (only seven of which are used) and t r i­
state buffer U2935 which drives the RAM address lines.
As the Character Counter addresses each RAM iocation,
a sequence of "d o t display cycles" is performed in which
the individual dots that make up the character are
positioned on the crt and turned on. The EOCH (end of
character) signal applied to U2885A prevents the counter
from incrementing until all dots of the character have
been displayed. As the last dot of a character is addressed,
the EOCH b it at pin 2 of U2855A goes LO. The next
GETDOT pulse increments U2940B, and the next RAM
location is addressed to start the display of the next
character. Space characters have the EOCH b it set LO fo r
the first " d o t" o f the character and merely advance the
Counter to the next character address w itho ut displaying
any dots. See the Character ROM description fo r further
explanation o f the EOCH bit.
Character ROM
Character ROM U2930 contains the horizontal and
vertical dot-position information fo r all o f the possible
characters (or cursor segments) that may be displayed.
The eight bits of character data from the Character RAM
are applied to the eight most-significant address inputs (A4
through A l l ) of the Character ROM and select a block of
dot-positioning data unique to the character to be displayed.
The Dot Counter increments the four least-significant
address lines (AO through A3), causing the ROM to output
a sequence of eight-bit words, each defining dot position
for the selected character.
The three least-significant bits of a ROM dot-data word
(DDO through DD2) select one of eight horizontal positions
fo r the dot w ithin an eight-by-sixteen character matrix (see
Figure 3-7). The next four bits (DD3 through DD6) define
the vertical position of the dot w ithin the matrix. These
dot-data bits are applied to the Horizontal and Vertical
Character DACs, where they are converted to the analog
voltages used to position the dot on the crt.
The last dot-data b it DD7 is the EOCH (end o f char­
acter) b it and, when LO, indicates that the last dot o f the
character is addressed. It is used to reset the Dot Counter
(via U2855B) and enables the Character Counter to be
incremented (via U2855A) after the last dot o f a character
has been displayed.
Two servicing jumpers, J401 and J402, have been pro-
v id e d to disable the Character ROM and force the DD7 b it
(EOCH) LO. In certain instances, these two conditions
may be useful when troubleshooting the Readout circuitry.
To prevent damage to the ROM output circuitry, J402
should only be installed after J401 is installed (to disable
the ROM).
Dot Counter
The Dot Counter consists of two four-bit counters
(U2870A and B), OR-gate U2835A, inverter U2980D, and
inverting input AND-gate U2855B. It sequences through a
block of addresses containing dot-position data fo r a
selected character. The Dot Counter is incremented when
a dot is finished (via Inverter U2980D) by the GETDOT
signal from the Dot Cycle Generator.
3-29