Tektronix 2445, Instruction Manual

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Theory of Operation—2445 Service
The counter increments through the block o f dot-
position data until the last byte of the block is encountered
(last dot). This last data byte has the EOCH (end of char­
acter) b it (DD7) set LO. The dot is positioned and dis­
played in the normal manner, but when the GETDOT
signal occurs fo r the next dot display cycle, the EOCH b it
is latched into U2905 and generates the EOCH1 (end of
character, delayed one dot) signal at U2905 pin 19. With
EOCH and EOCH1 both LO, the HI reset pulse produced
at pin 4 o f NOR-gate U2855B resets the counter and,
except fo r space characters, the EOCH b it returns HI. As
the reset is removed from the Dot Counter, it is reenabled
fo r display o f the next character. For space characters, the
EOCH b it w ill be detected as a LO when the first dot is
read from the Character ROM, and the Character Counter
w ill advance to the next character on the next rising edge of
GETDOT.
Counter U2870A and OR-gate U2835A enable char­
acters o f more than 16 dots to be displayed. Since most of
the readout characters are small, using 16 dots or less,
efficient data storage is achieved by storing the dot-position
data as 16 consecutive bytes. For displaying these smaller
characters, the fo ur bits from U2870B are sufficient to
address the 16 possible dot-position bytes.
When larger characters (up to 32 dots) are to be dis­
played, an additional b it of counter data must be used
to address the ROM. This fifth bit comes from U2870A
pin 3 and is ORed by U2835A w ith b it CDO from the
Character RAM. The block address fo r these larger char­
acters always has b it CDO set LO, so the counter b it from
U2870A pin 3 is in control o f the ROM address line at
pin 4 of U2930. When displaying these larger characters,
the dot count goes beyond 16 dots before the EOCH b it is
set LO. On the seventeenth character, the fifth counter b it
(pin 3 of U2870A) w ill go HI to address the next 16-byte
block o f character data in ROM U2930. The lower four bits
of the Dot Counter then sequence through this additional
block in the normal manner until the EOCH b it is encoun­
tered, resetting the counter.
Horizontal DAC
The Horizontal DAC generates the voltages used to
horizontally position dots of the readout display on the crt.
Five data bits (CAO through CA4) from the Character
Counter stage position a character to the correct column
in the display (32 possible columns across the crt), while
three data bits from Character ROM U2930 (DDO through
DD2) horizontally position the dots w ithin the eight-by-
sixteen character matrix (see Figure 3-7).
The eight bits o f position data are w ritten to the perma­
nently enabled DAC each time a new dot is requested by
the Dot Cycle Generator. The GETDOT signal applied to
pin 11 (Chip Select) enables the DAC to be w ritten into,
and the falling edge o f the 5-MHz clock applied to pin 12
(Write) writes the data at the eight DAC input pins into an
internal latch. The voltage at the DAC output pin changes
to reflect the data present in the latch.
Vertical Character DAC
The function o f Vertical Character DAC U2905 is
similar to that of the Horizontal DAC just described. It is
responsible fo r vertically positioning each character dot on
the crt. The Vertical DAC circuit is made up of five, D-type
flip-flops (contained w ithin U2905) and an accompanying
resistor weighting network. The outputs o f the flip-flop
source different amounts of current to a summing node
through a resistor weighting network.
The five data bits are latched into U2905 on the rising
edge of the GETDOT signal. One b it o f character address
data (CA5) from the Character Counter switches the
vertical display position between the upper and lower
readout display lines. When the display is to be in the
bottom line, b it CA5 is set LO. With CA5 LO, zener diode
VR2925 is biased o ff and a small current is sourced to the
summing node via R2925. Vertical position above this
reference is determined by dot data bits DD3 through DD6.
When the top line is to be displayed, the CA5 b it is set HI,
biasing VR2925 on. A larger current is now sourced into
the summing node via R2925 and enough voltage is devel­
oped across R2926 to move the display to the top row of
the crt. As before, the individual dots are then positioned
above this reference level by dot data bits DD3 through
DD6.
Mode Select Logic
The Mode Select Logic circuitry is composed of analog
switches U2800 and U2805, buffers U2820A and B, gates
U2810A, B, C, and D, U2900B and C, and part of U2905.
It controls the readout display mode by selecting which
deflection signals should drive the Horizontal and Vertical
Deflection Am plifiers during a readout display. Five display
modes are decoded by the Mode Select Logic: character
display, vertical cursor 0, vertical cursor 1, horizontal
cursor 0, and horizontal cursor 1.
For normal character displays, cursor select b it CA6
on U2800 pin 1 is LO. This LO signal passes through
analog switch U2800 and is latched into U2905 when the
GETDOT request from the Dot Cycle Generator goes HI.
This latched LO selects the character display mode by
forcing the outputs of U2900B and C and U2810A and
3-30