Tektronix 2445, Instruction Manual

Page: 58 / 351

Theory of Operation—2445 Service
Two analog control voltages set by the DAC and the
Channel 1 vertical position dc level m odify the differential
output signal at pins 9 and 10. The front-panel Channel 1
POSITION control supplies a dc level to U100 pin 17 that
vertically positions the Channel 1 display on the crt. A DC
Bal signal is applied to pin 2 of U100 from the DAC via the
sample-and-hold circuit composed of U160A and C177.
This DC Bal signal is a dc offset-null level that is determined
during the automatic DC Bal procedure. The offset value
is stored as a calibration constant in the EAROM and is
recalled at regular intervals to set the DC Bal level, holding
the Preamp in a dc balanced condition.
The Channel 1 VO LTS/DIV VAR control is monitored
by the Microprocessor during the front-panel scanning
routine. When the processor has determined where the
VO LTS/DIV VAR control is positioned, it causes DAC
U2234 (diagram 2) to produce a corresponding control
level and routes it to the VAR gain sample-and-hold circuit
composed o f U160D, C l 79, and associated components.
The control voltage at the output of U160D (pin 14) sets
the variable gain of the Preamp.
A pickoff amplifier internal to U100 conditions the
trigger signal and provides the proper signal level at pin 15
to drive the A/B Trigger Generator (U500, diagram 5).
The p ickoff point fo r the trigger signal is prior to the
addition of the vertical position offset, so the position of
the signal on the crt has no effect on the trigger operation.
However, the p icko ff point is after the DC Bal and Variable
gain signals have been added to the signal so both of these
functions w ill affect trigger operation.
Common-mode signals are rejected from the trigger
signal by the circuitry composed o f operational amplifier
U450A and associated components. The inverting input o f
U450A (pin 6) is connected to the common-mode point
between APO+ (pin 12) and TPO— (pin 15) o f U100. Any
common-mode signals present are inverted and applied to
a common-mode point between R451 and R453 to cancel
the signals from the differential output. A filte r network
composed of LR180 and the built-in circuit board capacitor
(5.6 pF) reduces trigger noise susceptibility. Trigger signals
fo r options are obtained by removing P100A and con­
necting the appropriate connector.
The Channel 1 input signal used to provide the hori­
zontal deflection fo r the X-Y displays is obtained from
U100 pin 11. The components between pin 11 and the
Horizontal O utput A m plifier provide phase compensation
of the signal. During instrument calibration, the delay
produced by C l 15, C l 16, L115, R115, and variable cap­
acitor Cl 18 is matched to the 78-ns delay of the vertical
delay line (DL100, diagram 6).
Channel 2 Preamplifier
Operation of Channel 2 Preamplifier U200 is nearly
identical to that of the Channel 1 Preamplifier just
described. The exceptions are that the output polarity of
the Channel 2 signal may be either normal or inverted and
that the signal obtained from the BPO+ output (pin 11) is
conditioned differently for a different purpose than in the
Channel 1 Preamplifier circuitry.
Inverting the Channel 2 signal for the CH 2 INVERT
feature is accomplished by biasing on different amplifiers.
The control data clocked into the internal control register
from pin 22 sets up the necessary switching.
The Channel 2 BPO+ signal at U200 pin 11 provides an
accurate representation of the Channel 2 signal at the
rear-panel CH 2 OUT connector. The BPO+ output signal
is reduced by divider R460 and R461 and is applied to the
emitter of Q460B. Transistor Q460B, configured as a diode,
provides thermal compensation for the bias voltage of
Q460A and reduces dc level shifts w ith varying temperature.
Emitter-follower Q460A provides the drive and impedance
matching to the CH 2 OUT connector and removes the
diode drop added by Q460B. Clamp diodes CR460 and
CR461 protect Q460B should a drive signal be accidentally
applied to the CH 2 OUT connector.
Channel 3 and Channel 4 Preamplifier
The functions provided by the Channel 3 and Channel
Preamplifier are similar to those provided by the Channel 1
and Channel 2 Preamplifiers. The single-ended CH 3 and
CH 4 input signals are converted to differential signals, and
vertical gain and vertical positioning information is added
to the output signals. Trigger pickoff signals are generated
fo r both channels and are routed to the Trigger hybrid.
Channel 3 and Channel 4 gains may be either 0.1 volt
per division or 0.5 volt per division. The logic levels of
control bits applied to U300 pin 30 (GA3) and pin 31
(GA4) from A uxiliary Control Register U140 sets the gain
o f the Channel 3 and Channel 4 Preamplifiers respectively.
Vertical positioning o f the Channel 3 and Channel 4 signals
on the crt is controlled by the variable voltage levels applied
to pin 29 (POS3) and pin 30 (POS4) from the front-panel
CH 3 and CH 4 POSITION potentiometers.
Dc offsets in the output signal due to any tracking
differences between the +5-V and the —5-V supply to
U300 are reduced by the tracking regulator circuit com­
posed o f U165A, Q190, and associated components.
Operational amplifier U165A and Q190 is configured so
that the output of voltage at the emitter o f Q190 follows
the —5-V supply applied to R198. This tracking arrange­
ment ensures that the supply voltages are of equal magni­
tudes to minimize dc offsets in the output signals.
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