Tektronix 2445, Instruction Manual

Page: 154 / 351

Maintenance— 2445 Service
LOOP through the Power Up Diagnostic Tests (except for
EAROM—Test 04). If a failure occurs, the cycle-failure data,
identifying the first failure encountered, is written to a specif­
ic location in the EAROM. Thereafter, at each power up, the
Diagnostic Monitor is automatically entered, and the failure
data is displayed even when the instrument is returned to
the normal operating configuration (CAL/NO CAL jumper in
the NO CAL position). Intepretation of the cycle failure data
is explained in the “Display Format” description provided
earlier in this section. The error data must be cleared from
the EAROM location to eliminate the CYCLE mode error
display.
Clearing the EAROM location is done by scrolling to the
EAROM CLEAR exerciser and pressing the following
switches in sequence:
COUPLING up (starts exerciser),
SOURCE down,
MODE down, then
COUPLING down.
When the EAROM CLEAR routine is successfully exe­
cuted, the cycle failure data and the diagonal line will disap­
pear from the display.
DISPLAY ROM HEADERS (Exerciser 04). This routine
displays the Standard Tektronix ROM Header of each sys­
tem ROM on the top line of the crt display. The readout line
has the following format:
CCCC PPPP SS AAAA
The definition of the format is as follows:
“CCCC” is a two-byte hexadecimal checksum.
“PPPP” is the four middle digits of the ROM part
number.
“SS” is the suffix of the ROM part number (version
number).
“AAAA” is the starting address of the ROM (address
where the ROM should be installed).
Pressing the COUPLING switch up increments the rou­
tine to the next ROM Header; pressing it down exits the
routine.
CONTROLLER LATCHES EXERCISER. This routine is
not user selectable, but it runs automatically when the Diag­
nostic Monitor is waiting for a key activation.
The routine first sets latches U2034 and U2134 (diagram
2). It then pulses the BSWPCLK line (pin 13 of U2596, dia­
gram 1), as a scope trigger, and rotates a “0” through 15 of
the 16 latched bits. Bit 16 is not set since it would reset
Interrupt Timer U2268 (diagram 1) and upset processor in­
terrupt timing. By externally triggering a test oscilloscope on
the BSWPCLK signal line and observing the shifted timing
relationships of the latched signals, proper operation of the
DAC latches may be verified.
NOP KERNEL EXERCISER. This exerciser is not a
firmware routine, but rather a forced hardware condition. It
is best suited for troubleshooting an inoperative Control
Board, as it exercises only the Microprocessor address bus
and the associated Address Decode circuitry. By moving
Jumper P503 (diagram 1) to the Diagnostic position. Data
Bus Buffers U2194 and U2294 are disabled, and the
Microprocessor is forced into a NOP (no operation) loop.
This causes the address on the address bus to be continu­
ously incremented for exercising the Address Decode cir­
cuitry. Troubleshooting of kernel addressing with an
oscilloscope or logic analyzer is then possible.
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