Tektronix 2445, Instruction Manual

Page: 53 / 351

Theory o f Operation—2445 Service
Analog Control
The operating mode and status of the 2445 require
that various analog voltages (for controlling instrument
functions) be set and updated. The digital values of the
controlling voltages are generated by the Microprocessor
and converted by the DAC. Analog multiplexers U2335 (on
diagram 2) and U170 (on diagram 4) route the DAC
voltages to sample-and-hold circuits that maintain the
control voltages between updates.
The Microprocessor writes three selection bits to register
U2034 that directs the DAC output to the appropriate
sample-and-hold circuit and charges a capacitor (or cap­
acitors) to the level of the DAC. When the processor
disconnects the DAC voltage from the sample-and-hold
circuit (by disabling the multiplexer) the capacitor(s)
remains charged and holds the control voltage near the
level set by the DAC. Due to the extremely high input
impedance of the associated operational amplifiers, the
charge on the capacitor(s) remains nearly constant between
updates.
EAROM
EAROM (electrically-alterable read-only memory)
U2008 provides nonvolatile storage for the calibration
constants and the power-down front-panel settings. When
power is applied to the 2445, the Microprocessor reads the
calibration constants and generates control voltages to set
up the analog circuitry. The front-panel settings that were
present at power-off are recalled to return the instrument
to that same operating mode.
The EAROM is a metal-nitride-oxide-semiconductor
device (MNOS) and requires a TTL-to-MNOS level shift of
the input control and data signals. A MNOS-to-TTL level
shift of the output data is also required. Inputs to U2008
are shifted to MNOS levels by U2118B through U2118F
and the associated components while output data is shifted
back to T T L levels by Q2025, U2118G, and the associated
components.
The EAROM data, address, and mode-control bits are
w ritten by the Microprocessor to five flip-flops o f register
U2208. The register outputs drive the level-shifting network
in the associated line. Three of thise latched bits define the
EAROM mode and w ill direct data into and out o f the
device. These three mode control bits are applied to pins 7,
8, and 9 o f U2008 and set the mode to either Accept
Address, Accept Data, Write Data, Read Data, or Shift-
Data-Out.
When writing data into the EAROM, the mode is first set
to Accept Address, then the address o f the location to be
altered is applied to the I/O port (pin 12) as a specially
encoded sequence o f 20 single bits via U2118C, R2020, and
CR2021. This sequence of bits is two, one-of-ten codes
where the position o f the first LO b it in the sequence
represents the most-significant b it of the address (in
decimal) and the position o f the second LO represents the
least-significant digit (see Figure 3-3).
The processor clocks each o f the 20 bits into the internal
address register by clocking U2008 pin 6 via the clock level
shifting network (U2118C and associated components).
d J
L
C2 |
r
C3 | ___________________________ r
I/O
PIN
*90^80^70^60*»^50*>|«40*«|«a30»»|*20*»|**10*»|«« 0 ►
1
< 9 **!** 8
+
7
+
6
+
5 4 3 2 ►}«■ 1
^
0 ►
note
:
addressing is via two consecutive one
-
of
-
ten
CODES. ADDRESS 99 IS ILLUSTRATED. 3831-1 1
3-11
Figure 3-3. Accept address timing.