Equipment Description
Page 4-12
Instruction Manual: evolution 5000 E5500 Mobile Contribution Encoder
ST.TM.E10033.3
Audio Input and Switch
The audio input consists of two channels, A and B, each capable of
AES/EBU digital audio and analogue audio. The analogue input stage
performs termination, gain control and Analogue to Digital (A/D)
conversion. The output of the A/D converter is I
2
S audio.
The digital input is received by an AES/EBU receive chip which converts
the input to I
2
S which is then passed through an Asynchronous Sample
Rate converter. The audio switch chooses from the sources and selects one
for compression.
Audio Encoders
The audio encoders are DSP circuits. The DSP has its own RAM and
communicates to the host via a dual port RAM. The input to the DSP is I
2
S
digital audio samples, the output is transport packets written into a First
In, First Out (FIFO) buffer.
Multiplexer
The function of the multiplexer is to take all of the individual sources of
packets within the unit and form them into a transport stream (video,
audio, SI, Teletext and data) which is output to the QPSK Modulator
Module.
4.7.8
E4 Video Compression Module (S8652)
Microprocessor
The S8652 E4 Video Compression Module is controlled by a
microprocessor. The microprocessor boots from the flash memory chips.
Associated with the microprocessor are an address decoder and local RAM.
The microprocessor communicates with the Base Board 3ASI
(Motherboard) via the dual port RAM. The interface is used to pass
information such as bit-rate and line standard between the Base Board
3ASI (Motherboard) microprocessor and the local microprocessor.
E4 Compression Chips
The E4 compression chips take video from the Base Board 3ASI
(Motherboard) via a 96-way edge connector. The two E4s (if both are
fitted) communicate with each other via a four-bit wide IPC interface. The
compressed video data is passed to the rate buffer.
Rate Buffer
The XILINX IC, (which controls the Video Compression Module), reads the
data from the rate buffer in single eight-bit wide words from each of the
eight field stores in turn. The data is packetised by the XILINX IC and the
resulting packets are written to the output FIFO where the multiplexer can
access them.
