Phytec phyCORE-i.MX 6, Hardware Manual

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phyCORE
®
-i.MX 6 [PCM-058]
iv ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
List of Tables
Table 1: Signal Types used in this Manual ................................................................... vi
Table 2: Abbreviations and Acronyms used in this Manual ..............................................vii
Table 3: Pinout of the phyCORE-Connector X1, Row A ................................................... 10
Table 4: Pinout of the phyCORE-Connector X1, Row B ................................................... 12
Table 5: Pinout of the phyCORE-Connector X1, Row C ................................................... 14
Table 6: Pinout of the phyCORE-Connector X1, Row D ................................................... 16
Table 7: Jumper Settings ....................................................................................... 21
Table 8: Boot Modes of the phyCORE-i.MX 6 ............................................................... 27
Table 9: Boot Configuration Pins at the phyCORE-Connector.......................................... 29
Table 10: EEPROM write protection states via J4 ........................................................... 32
Table 11: Location of the SD / MM Card Interface Signals................................................ 33
Table 12: Location of the UART Signals ....................................................................... 34
Table 13: Location of the USB OTG Signals................................................................... 35
Table 14: Location of the USB Host Signals.................................................................. 35
Table 15: Location of the Ethernet Signals .................................................................. 36
Table 16: Location of the RMII Interface Signals ........................................................... 38
Table 17: SPI Interface Signal Location....................................................................... 39
Table 18: I
2
C Interface Signal Location ....................................................................... 40
Table 19: I
2
S Interface Signal Location ....................................................................... 40
Table 20: CAN Interface Signal Location...................................................................... 41
Table 21: SATA Interface Signal Location .................................................................... 41
Table 22: PCIe Interface Signal Location ..................................................................... 42
Table 23: Location of GPIO Pins ................................................................................. 43
Table 24: Debug Interface Signal Location at phyCORE-Connector X1................................ 45
Table 25: Parallel Display Interface Signal Location....................................................... 46
Table 26: LVDS Display Interface Signal Location .......................................................... 47
Table 27: Supplementary Signals to support the Display Connectivity ............................... 47
Table 28: HDMI Interface Signal Location.................................................................... 48
Table 29: Camera Interface Parallel 0 (IPU1_CSI0) Signal Location................................... 51
Table 30: Camera Interface Parallel 1 (IPU2_CSI1) Signal Location................................... 52
Table 31: Camera Interface MIPI/CSI-2 Signal Location.................................................. 53
Table 32: Technical Specifications ............................................................................. 57
Table 33: Product Temperature Grades........................................................................ 58