Phytec phyCORE-i.MX 6, Hardware Manual

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phyCORE
®
-i.MX 6 [PCM-058]
32 ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
7.4.1 EEPROM Write Protection Control (J4)
Jumper J4 controls write access to the EEPROM (U11) device. Closing this jumper allows
write access to the device, while removing this jumper will cause the EEPROM to enter write
protect mode, thereby disabling write access to the device.
The following configurations are possible:
EEPROM Write Protection State J4
Write access allowed closed
EEPROM is write protected.
The protection can be changed by the EEPROM_WP signal (GPIO1_13)
open
Table 10: EEPROM write protection states via J4
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7.5 SPI Flash Memory (U9) )
The SPI Flash Memory of the phyCORE-i.MX 6 at U9 can be used to store configuration data
or any other general purpose data. Beside this it can also be used as boot device
20
and
recovery boot device
20
. The device is accessed through eCSPI1 SS1 on the i.MX 6. The
control registers for eCSPI1 are mapped between addresses 0x0200 8000 and 0x0200 BFFF.
Please see the
i.MX 6 Reference Manual for detailed information on the registers.
The SPI Flash can be write protected. The active low signal SPI_NOR_nWP/GPIO1_12
connects to GPIO1_12 of the i.MX 6 and allows to control the SPI Flash's write-protection.
As of the printing of this manual these SPI Flash devices generally have a life expectancy of
at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes
the SPI Flash a reliable and secure solution to store the first and second level bootloaders.
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: Defaults are in bold blue text
20
: The standard boot configuration selects the SPI Flash as recovery boot device. To use it as boot device the boot
configuration, or the eFUSEs must be changed.