Phytec phyCORE-i.MX 6, Hardware Manual

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phyCORE
®
-i.MX 6 [PCM-058]
12 ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
Pin # Signal ST Voltage Domain Description
B1 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
B2 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
B3 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
B4 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
B5 VDD_3V3_LOGIC REF_O VDD_3V3_LOGIC Logic reference voltage output
B6 GND - - Ground 0 V
B7 X_SD3_CLK O VDD_3V3_LOGIC uSDHC3 clock
B8 X_SD3_DATA1 I/O VDD_3V3_LOGIC uSDHC3 data 1
B9 X_SD3_DATA3 I/O VDD_3V3_LOGIC uSDHC3 data 3
B10 X_SD3_DATA4 I/O VDD_3V3_LOGIC uSDHC3 data 4
B11 X_SD3_DATA6 I/O VDD_3V3_LOGIC uSDHC3 data 6
B12 GND - - Ground 0 V
B13 X_SD1_CLK O VDD_3V3_LOGIC uSDHC1 clock
B14 X_SD1_CMD O VDD_3V3_LOGIC uSDHC1 command
B15 X_SD1_DATA1 I/O VDD_3V3_LOGIC uSDHC1 data 1
B16 X_SD1_DATA3 I/O VDD_3V3_LOGIC uSDHC1 data 3
B17 GND - - Ground 0 V
B18 X_UART3_TX_DATA O VDD_3V3_LOGIC UART3 serial transmit signal
B19 X_ENET_MDIO I/O VDD_ENET_IO ENET management data I/O
B20 X_ENET_MDC O VDD_ENET_IO ENET management data clock
B21 X_UART2_TX_DATA O VDD_3V3_LOGIC UART2 serial transmit signal
B22 GND - - Ground 0 V
B23 X_I2C1_SCL OC_BI VDD_3V3_LOGIC I2C1 clock
B24 X_I2C1_SDA OC_BI VDD_3V3_LOGIC I2C1 data
B25 X_ECSPI1_MISO I/O VDD_3V3_LOGIC eCSPI1 master input/slave output
B26 X_EIM_DA14 I/O VDD_3V3_LOGIC EIM address/data 14
9; 10
B27 X_EIM_DA15 I/O VDD_3V3_LOGIC EIM address/data 15
9; 10
B28 GND - - Ground 0 V
B29 X_CSI1_DATA19 I VDD_3V3_LOGIC IPU2_CSI1 data 19
8
B30 X_CSI1_DATA18 I VDD_3V3_LOGIC IPU2_CSI1 data 18
8
B31 X_CSI1_DATA17 I VDD_3V3_LOGIC IPU2_CSI1 data 17
8
B32 X_CSI1_DATA16 I VDD_3V3_LOGIC IPU2_CSI1 data 16
8
B33 GND - - Ground 0 V
B34 X_CSI1_DATA15 I VDD_3V3_LOGIC IPU2_CSI1 data 15
8
B35 X_CSI1_DATA14 I VDD_3V3_LOGIC IPU2_CSI1 data 14
8
B36 X_CSI1_PIXCLK O VDD_3V3_LOGIC IPU2_CSI1 pixel clock
8
Table 4: Pinout of the phyCORE-Connector X1, Row B