Phytec phyCORE-i.MX 6, Hardware Manual

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Power
©
PHYTEC Messtechnik GmbH 2016 L-808e_2
23
4.2.1 Power Domains
External voltages:
•
VDD_3V3 3.3 V main supply voltage
•
USB0_VBUS USB0 Bus voltage, must be supplied with 5 V if USB0 is used
•
USB1_VBUS USB1 Bus voltage, must be supplied with 5 V if USB1 is used
•
VDD_BAT Backup supply (connected to PMIC_VBBAT or VDD_MX6_SNVS via
J3 (
Table 7 ))
Internally generated voltages: VDD_MX6_ARM (1.375
V), VDD_MX6_SOC (1.375 V),
VDD_3V3_LOGIC (3.3 V), VDD_ETH_IO (2.5 V) VDD_MX6_SNVS (3.0 V), VDD_MX6_HIGH
(3.0 V), VDD_eMMC_1V8 (1.8 V) VDD_ETH_1V2 (1.2
V), VDD_DDR3_1V5 (1.5 V),
DDR3_VREF (0.75 V)
•
VDD_MX6_ARM: i.MX 6 core (VDDARM_IN, VDDARM23_IN)
(1.375 V)
•
VDD_MX6_SOC: i.MX 6 SOC (VDDSOC_IN)
(1.375 V)
•
VDD_MX6_HIGH: i.MX 6 internal regulator (VDDHIGH_IN)
(3.0 V)
•
VDD_MX6_SNVS: i.MX 6 backup supply (VDD_SNVS_IN)
(3.0 V)
•
VDD_ETH_IO: i.MX 6 RGMII supply (NVCC_RGMII, NVCC_ENET
13
),
(2.5 V) Ethernet PHY RGMII IO supply
•
VDD_ETH_1V2: Ethernet PHY core voltage
(1.2 V)
•
VDD_DDR3_1V5: i.MX 6 DDR interface (NVCC_DRAM), RAM devices
(1.5 V)
•
VDD_eMMC_1V8: 1.8V eMMC supply
(1.8 V)
•
DDR3_VREF: i.MX 6 DDR3 reference voltage (DRAM_VREF), RAM devices
(0.75 V) reference voltage
•
VDD_3V3_LOGIC: i.MX 6 pad supply (NVCC_NANDF, NVCC_JTAG, NVCC_LCD,
(3.3 V) NVCC_CSI, NVCC_EIM, NVCC_SD, NVCC_GPIO, (NVCC_ENET
13
)),
I
2
C EEPROM, SPI Flash, NAND Flash, eMMC, Ethernet PHY,
User LED, reference output X1B5
13
: NVCC_ENET is connected via jumper J1 and can alternatively be supplied by VDD_3V3_LOGIC ( section 9.4.4 )