Phytec phyCORE-i.MX 6, Hardware Manual

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Power
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PHYTEC Messtechnik GmbH 2016 L-808e_2
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4.3 Supply Voltage for external Logic
The voltage level of the phyCORE’s logic circuitry is VDD_3V3_LOGIC (3.3 V) which is
derived from the main input voltage VDD_3V3 of the SOM. In order to follow the power-up
and power–down sequencing mandatory for the i.MX 6 external devices have to be
supplied by the I/O supply voltage VDD_3V3_LOGIC which is brought out at pin X1B5 of the
phyCORE-Connector. Use of VDD_3V3_LOGIC ensures that external components are only
supplied when the supply voltages of the i.MX 6 are stable.
Caution!
•
The current draw for VDD_3V3_LOGIC must not exceed 500 mA. Consequently this
voltage should only be used as reference, or supply voltage for level shifters, and not
for supplying purpose. If devices with a higher power consumption are to be connected
to the phyCORE-i.MX 6 their supply voltage should be switched on and off by use of the
X_3V3_GOOD signal. This way the power-up and power–down sequencing will be
considered even if the devices are not supplied directly by VDD_3V3_LOGIC.
If used to control, or supply bus switches on the phyCORE side VDD_3V3_LOGIC also serves
to strictly separate the supply voltages generated on the phyCORE-i.MX 6 and the supply
voltages used on the carrier board/custom application. That way, voltages at the IO pins of
the phyCORE-i.MX 6 which are sourced from the supply voltage of peripheral devices
attached to the SOM are avoided. These voltages can cause a current flow into the
controller especially if peripheral devices attached to the interfaces of the i.MX 6 are
supposed to be powered while the phyCORE-i.MX 6 is in suspend mode, or turned off. The
bus switches can either be supplied by VDD_3V3_LOGIC on the phyCORE side, or the bus
switches' output enable to the SOM can be controlled by X_3V3_GOOD to prevent these
voltages from occurring.
Use of level shifters supplied with VDD_3V3_LOGIC allows converting the signals according
to the needs on the custom target hardware. Alternatively signals can be connected to an
open drain circuitry with a pull-up resistor attached to VDD_3V3_LOGIC.
4.4 Backup Power (PMIC_VBAT/VDD_MX6_SNVS)
To backup the PMIC's RTC and some of its critical registers, or the i.MX 6's low power
domain (SNVS_LP) and its RTC, a secondary voltage source of 3 V can be attached to the
phyCORE-i.MX 6 at pin X1A5. Jumper J3 selects either the backup voltage domain
PMIC_VBAT (J3:1+2) or the i.MX6's voltage domain VDD_MX6_SNVS (J3:2+3) to be
supplied when the primary system power (VDD_3V3) is removed.