Phytec phyCORE-i.MX 6, Hardware Manual

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LVDS Camera Interface
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PHYTEC Messtechnik GmbH 2016 L-808e_2
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Using the phyCORE's camera interface Parallel 1, together with an I²C bus facilitates easy
implementation of a CMOS camera interface, e.g. a phyCAM-P or a phyCAM-S+ interface, on
a custom carrier board (
section 15.4 ).
15.3 MIPI/CSI-2 Camera Interface
The MIPI/CSI-2 camera interface of the i.MX 6 extends to the phyCORE-Connector X1 with 4
data lanes and one clock lane.
Note:
It is not possible to use the MIPI/CSI-2 interface and the IPU1_CSI0 or IPU2_CSI1 interface
at the same time.
The following table shows the location of the signals.
Pin # Signal ST Voltage Domain Description
X1C30 X_CSI_D0P CSI2_I i.MX 6 internal MIPI/CSI data0+
X1C31 X_CSI_D0M CSI2_I i.MX 6 internal MIPI/CSI data0-
X1D27 X_CSI_D1P CSI2_I i.MX 6 internal MIPI/CSI data1+
X1D28 X_CSI_D1M CSI2_I i.MX 6 internal MIPI/CSI data1-
X1C33 X_CSI_D2P CSI2_I i.MX 6 internal MIPI/CSI data2+
X1C34 X_CSI_D2M CSI2_I i.MX 6 internal MIPI/CSI data2-
X1D29 X_CSI_D3P CSI2_I i.MX 6 internal MIPI/CSI data3+
X1D30 X_CSI_D3M CSI2_I i.MX 6 internal MIPI/CSI data3-
X1C35 X_CSI_CLK0P CSI2_I i.MX 6 internal MIPI/CSI clock+
X1C36 X_CSI_CLK0M CSI2_I i.MX 6 internal MIPI/CSI clock-
Signals that can be optionally used with the camera ports
X1B23 X_I2C1_SCL OC_BI VDD_3V3_LOGIC
I2C1 clock
X1B24 X_I2C1_SDA OC_BI VDD_3V3_LOGIC I2C1 data
X1D16 X_CCM_CLKO1 O VDD_3V3_LOGIC
CCM clock output 1 (Camera0
MCLK)
Table 31: Camera Interface MIPI/CSI-2 Signal Location
Use of the I²C bus and the camera clock signal allows to directly connect a MIPI/CSI-2
camera module.