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Debug

Interfaces

PHYTEC Messtechnik GmbH 2016 L-808e_2

Debug Interface

The phyCORE-i.MX 6 is equipped with a JTAG interface for downloading program code into
the external flash, internal controller RAM or for debugging programs currently executing.

Table 24

shows the location of the JTAG pins on the phyCORE-Connector X1.

Pin #

Signal

Voltage Domain

Description

X1C28 X_JTAG_TMS

VDD_3V3_LOGIC JTAG

TMS

X1C29 X_JTAG_TDO

VDD_3V3_LOGIC JTAG

TDO

X1D23 X_JTAG_TCK

VDD_3V3_LOGIC JTAG

clock

input

X1D25 X_JTAG_TRSTB

VDD_3V3_LOGIC

JTAG reset input (low active)

X1D26 X_JTAG_TDI

VDD_3V3_LOGIC JTAG

TDI

Table 24:

Debug Interface Signal Location at phyCORE-Connector X1

Summary of Contents for phyCORE-i.MX 6

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE i MX 6 Hardware Manual Document No L 808e_2 SOM Prod No PCM 058 SOM PCB No 1429 3 Edition August 2016...

Page 2: ...PHYTEC Messtechnik GmbH D 55129 Mainz Rights including those of translation reprint broadcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part...

Page 3: ...26 6 System Configuration and Booting 27 6 1 Boot Mode Selection 27 6 2 Boot Device Selection and Configuration 28 7 System Memory 30 7 1 DDR3 SDRAM U4 U7 30 7 2 NAND Flash Memory U12 31 7 3 eMMC Flas...

Page 4: ...Interfaces 49 15 1 Parallel 0 Camera Interface CSI0 of IPU 1 51 15 2 Parallel 1 Camera Interface CSI1 of IPU 2 52 15 3 MIPI CSI 2 Camera Interface 53 15 4 Utilizing the Camera Interfaces on a Carrier...

Page 5: ...e 8 Powering Scheme of the phyCORE i MX 6 24 Figure 9 User LED Location top view 44 Figure 10 Camera Connectivity of the i MX 6 Solo DualLite 49 Figure 11 Camera Connectivity of the i MX 6 Dual Core Q...

Page 6: ...Signals 35 Table 15 Location of the Ethernet Signals 36 Table 16 Location of the RMII Interface Signals 38 Table 17 SPI Interface Signal Location 39 Table 18 I2 C Interface Signal Location 40 Table 19...

Page 7: ...ant for software development Please refer to the i MX 6 Reference Manual if such information is needed to connect customer designed applications Conventions The conventions used in this manual are as...

Page 8: ...wn 5V_PD LVDS Input Differential line pairs 100 Ohm LVDS level input LVDS_I LVDS Output Differential line pairs 100 Ohm LVDS level output LVDS_O TMDS Output Differential line pairs 100 Ohm TMDS level...

Page 9: ...IRAM Internal RAM the internal static RAM on the NXP Semiconductor i MX 6 microcontroller J Solder jumper these types of jumpers require solder equipment to remove and place JP Solderless jumper these...

Page 10: ...of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to re invent microcontroller circuitry Furthermore much of the value of the phyCORE module...

Page 11: ...or http www phytec eu europe support registration html For technical support and additional information concerning your product please visit the support section of our web site which provides product...

Page 12: ...electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header row...

Page 13: ...y evaluating long livety of parts during design in phase Ensure availability of equivalent second source parts Stay in close contact with part vendors to be aware of roadmap strategies Change manageme...

Page 14: ...phyCORE i MX 6 PCM 058 xii PHYTEC Messtechnik GmbH 2016 L 808e_2...

Page 15: ...e 0402 packaged SMD components and laser drilled microvias are used on the boards providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own des...

Page 16: ...direct connection to an existing Ethernet network or without on board transceiver and provision of the RMII signals at TTL level at the phyCORE Connector instead3 I2 C interface Two SPI interfaces PC...

Page 17: ...Introduction PHYTEC Messtechnik GmbH 2016 L 808e_2 3 1 2 Block Diagram Figure 1 Block Diagram of the phyCORE i MX 65 5 The specified direction indicated refers to the standard phyCORE use of the pin...

Page 18: ...116 C284 C66 C283 C302 R123 R14 R21 R19 C40 C67 C65 R20 R38 C42 C294 C43 C298 C296 R139 R135 R140 R146 R136 R141 C121 C49 C297 R149 C2 C1 R24 R25 R121 R129 R114 R115 R13 R109 R150 C95 C100 R125 R124 C...

Page 19: ...U15 R23 R30 C186 C194 C282 C98 C207 C168 R10 R103 R128 R72 C125 C45 R73 C169 C274 C295 C130 R78 R87 C299 C286 C304 C27 C142 C62 C173 C152 C174 C256 R75 C136 R126 R35 C217 C269 C181 C182 R81 C197 R32 C...

Page 20: ...ower supply and at least the matching number of GND pins Corresponding GND X1 A6 A11 A16 A21 B6 B12 B17 B22 Please refer to section 2 for information on additional GND Pins located at the phyCORE Conn...

Page 21: ...numbered matrix pin X1C1 is thus covered with the corner of the phyCORE i MX 6 The numbering scheme is always in relation to the PCB as viewed from above even if all connector contacts extend to the...

Page 22: ...used to configure the boot mode for specific boot options please make sure that these signals are not driven by any device on the baseboard during reset The signals which may affect the boot configura...

Page 23: ...order to utilize a specific pin s alternative function the corresponding registers must be configured within the appropriate driver of the BSP The following tables describe the full set of signals av...

Page 24: ...IC UART2 serial data receive A18 X_UART3_RX_DATA I VDD_3V3_LOGIC UART3 serial data receive A19 X_UART3_CTS_B O VDD_3V3_LOGIC UART3 clear to send output A20 X_UART3_RTS_B I VDD_3V3_LOGIC UART3 request...

Page 25: ...D_3V3_LOGIC DISP0 data 16 A51 GND Ground 0 V A52 X_LCD_DATA14 O VDD_3V3_LOGIC DISP0 data 14 A53 X_LCD_DATA13 O VDD_3V3_LOGIC DISP0 data 13 A54 X_LCD_DATA11 O VDD_3V3_LOGIC DISP0 data 11 A55 X_LCD_DATA...

Page 26: ..._LOGIC uSDHC1 data 3 B17 GND Ground 0 V B18 X_UART3_TX_DATA O VDD_3V3_LOGIC UART3 serial transmit signal B19 X_ENET_MDIO I O VDD_ENET_IO ENET management data I O B20 X_ENET_MDC O VDD_ENET_IO ENET mana...

Page 27: ...B54 X_LCD_DATA15 O VDD_3V3_LOGIC DISP0 data 15 B55 X_LCD_DATA12 O VDD_3V3_LOGIC DISP0 data 12 B56 X_LCD_DATA10 O VDD_3V3_LOGIC DISP0 data 10 B57 X_LCD_DATA09 O VDD_3V3_LOGIC DISP0 data 9 B58 GND Groun...

Page 28: ...X_SPDIF_OUT O VDD_3V3_LOGIC SPDIF output10 C17 X_PWM1_OUT O VDD_3V3_LOGIC PWM1 output10 C18 X_USB_OTG_ID I VDD_3V3_LOGIC USB OTG ID Pin C19 X_USB_OTG_VBUS PWR_I 5 V USB OTG VBUS input C20 X_USB_OTG_P...

Page 29: ...CSI0 data 8 C52 X_CSI0_DAT6 I VDD_3V3_LOGIC IPU1_CSI0 data 6 C53 X_CSI0_DAT5 I VDD_3V3_LOGIC IPU1_CSI0 data 5 C54 GND Ground 0 V C55 X_CSI0_DAT4 I VDD_3V3_LOGIC IPU1_CSI0 data 4 C56 X_CSI0_PIXCLK O VD...

Page 30: ...X_USB_OTG_CHD_B O VDD_3V3_LOGIC USB OTG charger detection D18 GND Ground 0 V D19 X_USB_OTG_DP USB_I O i MX 6 internal USB OTG data D20 X_USB_OTG_DN USB_I O i MX 6 internal USB OTG data D21 X_USB_OTG_...

Page 31: ...GIC I2 S AUD5 receive data D53 X_AUD5_TXC I O VDD_3V3_LOGIC I2 S AUD5 transmit clock D54 X_AUD5_TXFS I O VDD_3V3_LOGIC I2 S AUD5 frame sync D55 GND Ground 0 V D56 X_AUD5_TXD I O VDD_3V3_LOGIC I2 S AUD...

Page 32: ...positions and functions A detailed description of each solder jumper can be found in the applicable chapter listed in the table Note Jumpers not listed should not be changed as they are installed wit...

Page 33: ...Jumpers PHYTEC Messtechnik GmbH 2016 L 808e_2 19 Figure 6 Jumper Locations top view J6 J3 J4...

Page 34: ...D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B...

Page 35: ...anged by the EEPROM_WP signal GPIO1_13 0R 0402 7 4 1 J3 J3 defines which backup domain is supplied by the backup voltage input X1A5 1 2 PMIC backup domain is supplied 2 3 i MX 6 low power domain SNVS_...

Page 36: ...and at least the matching number of GND pins Corresponding GND X1 A6 A11 A16 A21 B6 B12 B17 B22 Please refer to section 2 for information on additional GND Pins located at the phyCORE Connector X1 Ca...

Page 37: ...DARM23_IN 1 375 V VDD_MX6_SOC i MX 6 SOC VDDSOC_IN 1 375 V VDD_MX6_HIGH i MX 6 internal regulator VDDHIGH_IN 3 0 V VDD_MX6_SNVS i MX 6 backup supply VDD_SNVS_IN 3 0 V VDD_ETH_IO i MX 6 RGMII supply NV...

Page 38: ...2016 L 808e_2 Figure 8 Powering Scheme of the phyCORE i MX 6 VDD_3V3 DA9062 VDD_MX6_ARM VDD_MX6_SOC VDD_DDR3_1V5 Switch VDD_3V3_LOGIC VDD_ETH_1V2 Switching regulators LDOs VDD_ETH_IO VDD_eMMC_1V8 VDD...

Page 39: ...ate the supply voltages generated on the phyCORE i MX 6 and the supply voltages used on the carrier board custom application That way voltages at the IO pins of the phyCORE i MX 6 which are sourced fr...

Page 40: ...EQ signal of the DA9062 PMIC which triggers a hard reset of the module with a debouncing time of 10 24 ms When used as reset output the nRESET signal of the DA9062 PMIC is brought out to allow resetti...

Page 41: ...of the eFUSEs and or the corresponding GPIO input pins BOOT_CFGx 7 0 6 1 Boot Mode Selection The boot mode of the i MX 6 microcontroller is determined by the configuration of two boot mode inputs BOOT...

Page 42: ...SEs BOOT_CFGx 7 0 if the BT_FUSE_SEL fuse is not blown Table 9 lists the eFUSEs BOOT_CFGx 7 0 and the corresponding input pins On the phyCORE i MX 6 the GPIOs have 10 k pull up and pull down resistors...

Page 43: ...X_EIM_DA14 I O 3 3 V EIM address data 14 BCFG2 7 X1B27 X_EIM_DA15 I O 3 3 V EIM address data 15 BCFG3 0 X1B36 X_CSI1_PIXCLK O 3 3 V IPU2_CSI1 pixel clock BCFG3 1 X1A27 X_CSI1_DATA12 I 3 3 V IPU2_CSI1...

Page 44: ...DDR interface called Multi Mode DDR Controller MMDC of the i MX 6 microcontroller The DDR3 memory is accessible starting at address 0x1000 0000 Typically the DDR3 SDRAM initialization is performed by...

Page 45: ...Alternatively to the NAND flash memory at U12 an eMMC can be populated at U14 The eMMC device is programmable with 3 3 V No dedicated programming voltage is required The eMMC Flash memory is connected...

Page 46: ...de this it can also be used as boot device20 and recovery boot device20 The device is accessed through eCSPI1 SS1 on the i MX 6 The control registers for eCSPI1 are mapped between addresses 0x0200 800...

Page 47: ...SDHC3 command X1A8 X_SD3_DATA0 I O VDD_3V3_LOGIC uSDHC3 data 0 X1A9 X_SD3_DATA2 I O VDD_3V3_LOGIC uSDHC3 data 2 X1A10 X_SD3_DATA5 I O VDD_3V3_LOGIC uSDHC3 data 5 X1A12 X_SD3_DATA7 I O VDD_3V3_LOGIC uS...

Page 48: ...6 SATA PHY 10 PCI Express Gen 2 0 extended directly from the i MX 6 PCIe PHY The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers 9 1...

Page 49: ...MX 6 internal USB OTG data X1D21 X_USB_OTG_OC I VDD_3V3_LOGIC USB OTG overcurrent input Table 13 Location of the USB OTG Signals Caution X_USB_OTG_VBUS must be supplied with 5 V for proper USB functi...

Page 50: ...3 X_ETH0_A TX0 ETH_O VDD_3V3_LOGIC ETH0 data A transmit X1C5 X_ETH0_C ETH_I O VDD_3V3_LOGIC ETH0 data C only GbE X1C6 X_ETH0_C ETH_I O VDD_3V3_LOGIC ETH0 data C only GbE X1C7 X_ETH0_LED0 OC VDD_3V3_LO...

Page 51: ...he datasheet of the Ethernet PHY when designing the Ethernet transformer circuitry or request the schematic of the applicable carrier board phyBOARD Mira i MX 6 as reference 9 4 2 Software Reset of th...

Page 52: ...3 3 V instead of VDD_ETH_IO 2 5 V Table 7 Pin Signal ST Voltage Domain Description X1A65 X_ENET_REFCLK I VDD_3V3_LOGIC ENET RMII reference clock X1A67 X_ENET_TXER O VDD_3V3_LOGIC ENET MII transmit er...

Page 53: ...tage Domain Description X1A22 X_ECSPI1_SCLK O VDD_3V3_LOGIC eCSPI1 clock X1A23 X_ECSPI1_MOSI I O VDD_3V3_LOGIC eCSPI1 master output slave input X1A24 X_ECSPI1_SS0 O VDD_3V3_LOGIC eCSPI1 chip select 02...

Page 54: ...erface SSI The Synchronous Serial Interface SSI of the phyCORE i MX 6 is a full duplex serial interface that allows to communicate with a variety of serial devices such as standard codecs digital sign...

Page 55: ...rialized ATA data link interface compliant with SATA Revision 3 0 physical layer complies with SATA Revision 2 5 which supports data rates of up to 3 0 Gbit s The interface includes an internal DMA en...

Page 56: ...lease refer to the schematic of a suitable Phytec carrier board e g phyBOARD Mira i MX 6 for a circuit example Table 22 shows the position of the PCIe signals on the phyCORE Connector X1 Pin Signal ST...

Page 57: ...B1 O VDD_3V3_LOGIC EIM enable byte 1 GPIO2_29 X1C16 X_SPDIF_OUT O VDD_3V3_LOGIC SPDIF output GPIO7_12 X1C17 X_PWM1_OUT O VDD_3V3_LOGIC PWM1 output GPIO1_09 X1D13 X_KEY_COL2 I VDD_3V3_LOGIC Keypad colu...

Page 58: ...2016 L 808e_2 11 User LED The phyCORE i MX 6 provides one green user LED D1 on board It can be controlled by setting GPIO1_04 to the desired output level A high level turns the LED on a low level tur...

Page 59: ...rrently executing Table 24 shows the location of the JTAG pins on the phyCORE Connector X1 Pin Signal ST Voltage Domain Description X1C28 X_JTAG_TMS I VDD_3V3_LOGIC JTAG TMS X1C29 X_JTAG_TDO O VDD_3V3...

Page 60: ...GIC DISP0 data 6 X1A58 X_LCD_DATA05 O VDD_3V3_LOGIC DISP0 data 5 X1A59 X_LCD_DATA03 O VDD_3V3_LOGIC DISP0 data 3 X1A60 X_LCD_DATA00 O VDD_3V3_LOGIC DISP0 data 0 X1A62 X_LCD_ENABLE O VDD_3V3_LOGIC DISP...

Page 61: ...ernal LVDS0 clock X1D59 X_LVDS0_CLK LVDS_O i MX 6 internal LVDS0 clock X1D60 X_LVDS0_TX2 LVDS_O i MX 6 internal LVDS0 data 2 X1D61 X_LVDS0_TX2 LVDS_O i MX 6 internal LVDS0 data 2 X1C66 X_LVDS1_CLK LVD...

Page 62: ...X1C39 X_HDMI_CLKP TDMS_O i MX 6 internal HDMI clock X1C40 X_HDMI_CLKM TDMS_O i MX 6 internal HDMI clock X1C41 X_HDMI_D1P TDMS_O i MX 6 internal HDMI data1 X1C42 X_HDMI_D1M TDMS_O i MX 6 internal HDMI...

Page 63: ...te microcontrollers are equipped with one parallel camera port IPU1_CSI0 and one image processing units version 3H IPU 1 to process the signals from the parallel or the MIPI camera interface Figure 10...

Page 64: ...XCLK The MIPI CSI 2 interface connects to the phyCORE Connector with 5 lanes Figure 12 Figure 12 Camera Interfaces at the phyCORE Connector Parallel 0 CSI0 of IPU 1 Parallel 1 CSI1 of IPU 2 and MIPI C...

Page 65: ...VDD_3V3_LOGIC IPU1_CSI0 data 7 X1C52 X_CSI0_DAT6 I VDD_3V3_LOGIC IPU1_CSI0 data 6 X1C53 X_CSI0_DAT5 I VDD_3V3_LOGIC IPU1_CSI0 data 5 X1C55 X_CSI0_DAT4 I VDD_3V3_LOGIC IPU1_CSI0 data 4 X1C56 X_CSI0_PIX...

Page 66: ...DD_3V3_LOGIC IPU2_CSI1 data 625 X1B41 X_CSI1_DATA05 I VDD_3V3_LOGIC IPU2_CSI1 data 525 X1B42 X_CSI1_DATA04 I VDD_3V3_LOGIC IPU2_CSI1 data 425 X1A33 X_CSI1_DATA03 I VDD_3V3_LOGIC IPU2_CSI1 data 325 X1A...

Page 67: ...PI CSI data0 X1C31 X_CSI_D0M CSI2_I i MX 6 internal MIPI CSI data0 X1D27 X_CSI_D1P CSI2_I i MX 6 internal MIPI CSI data1 X1D28 X_CSI_D1M CSI2_I i MX 6 internal MIPI CSI data1 X1C33 X_CSI_D2P CSI2_I i...

Page 68: ...igure 14 or as MIPI CSI 2 interface Figure 13 Use of Parallel 0 CSI0 of IPU 1 and Parallel 1 CSI1 of IPU 2 as phyCAM P interface Figure 14 Use of Parallel 0 CSI0 of IPU 1 and Parallel 1 CSI1 of IPU 2...

Page 69: ...phyCORE i MX 6 i MX 6 VDD_SNVS_IN For proper operation of the tamper detection an always ON power supply coin cell battery or memory backup capacitor must be connected to the VDD_MX6_SNVS power input...

Page 70: ...dimensions of the phyCORE i MX 6 are represented in Figure 15 The module s profile is max 10 mm thick with a maximum component height of 3 0 mm on the bottom connector side of the PCB and approximate...

Page 71: ...C to 125 C Operating temperature refer to section 17 1 Humidity 95 r F not condensed Operating voltage VCC 3 3 V 5 Power consumption Linux prompt only typical 1 9 W QT Demo typical 4 1 W 4 Cores full...

Page 72: ...below describes these grades in detail These grades describe a set of components which in combination add up to a useful set of product options with different temperature grades This enables us to ma...

Page 73: ...d below The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum com...

Page 74: ...de support knowledge database soms system on modules phycore phycore imx 6 or http www phytec eu europe support faq faq phyCORE i MX 6 html 3 the link Carrier Board within the category Dimensional Dra...

Page 75: ...6 Footprint of the phyCORE i MX 6 Ref Des D2 6mm D5mm 19 15mm 32 2mm 1 8mm 34mm 37mm 40mm 44mm 47mm 50mm 3mm 3mm 23 61mm mounting hole PAD A tolerance of 0 1 mm applies to all indicated measures excep...

Page 76: ...ing connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Caution If any modifications t...

Page 77: ...3 19 Revision History Date Version numbers Changes in this manual 04 06 2015 Manual L 808e_1 First edition Describes the phyCORE i MX 6 PCB Version 1429 1 04 08 2016 Manual L 808e_2 Second edition Des...

Page 78: ...phyCORE i MX 6 PCM 058 64 PHYTEC Messtechnik GmbH 2016 L 808e_2...

Page 79: ...rotection 32 EMC x eMMC Flash 31 Ethernet 36 F Features 1 G General Purpose I Os 43 GND Connection 62 H Humidity 57 I I C EEPROM 31 I2 C Interface 40 I2 C Memory 21 I2 S 40 J J121 J321 J421 32 J621 JT...

Page 80: ...30 32 SPI Interface 39 Storage Temperature 57 Supply Voltage 22 System Configuration 27 System Memory 30 System Power 22 T Tamper Detection 55 Technical Specifications 56 U U11 31 U12 31 U14 31 U16 22...

Page 81: ...phyCORE i MX 6 Document number L 808e_2 August 2016 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC...

Page 82: ...Published by PHYTEC Messtechnik GmbH 2016 Ordering No L 808e_2 Printed in Germany...

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