Phytec phyCORE-i.MX 6, Hardware Manual

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Pin Description
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PHYTEC Messtechnik GmbH 2016 L-808e_2
11
Pin # Signal ST Voltage Domain Description
A37 X_CSI1_DATA01 I VDD_3V3_LOGIC IPU2_CSI1 data 1
8
A38 X_CSI1_DATA00 I VDD_3V3_LOGIC IPU2_CSI1 data 0
8
A39 X_CSI1_VSYNC I VDD_3V3_LOGIC IPU2_CSI1 vertical sync
8
A40 X_CSI1_HSYNC I VDD_3V3_LOGIC IPU2_CSI1 horizontal sync
8
A41 GND - - Ground 0 V
A42 X_EIM_BCLK O VDD_3V3_LOGIC EIM burst block
10
A43 X_ECSPI2_MISO I/O VDD_3V3_LOGIC eCSPI2 master input/slave output
A44 X_ECSPI2_SS1 I/O VDD_3V3_LOGIC eCSPI2 chip select 1
8
A45 X_ECSPI2_SS0 I/O VDD_3V3_LOGIC eCSPI2 chip select 0
8
A46 GND - - Ground 0 V
A47 X_LCD_DATA22 O VDD_3V3_LOGIC DISP0 data 22
A48 X_LCD_DATA21 O VDD_3V3_LOGIC DISP0 data 21
A49 X_LCD_DATA19 O VDD_3V3_LOGIC DISP0 data 19
A50 X_LCD_DATA16 O VDD_3V3_LOGIC DISP0 data 16
A51 GND - - Ground 0 V
A52 X_LCD_DATA14 O VDD_3V3_LOGIC DISP0 data 14
A53 X_LCD_DATA13 O VDD_3V3_LOGIC DISP0 data 13
A54 X_LCD_DATA11 O VDD_3V3_LOGIC DISP0 data 11
A55 X_LCD_DATA08 O VDD_3V3_LOGIC DISP0 data 8
A56 GND - - Ground 0 V
A57 X_LCD_DATA06 O VDD_3V3_LOGIC DISP0 data 6
A58 X_LCD_DATA05 O VDD_3V3_LOGIC DISP0 data 5
A59 X_LCD_DATA03 O VDD_3V3_LOGIC DISP0 data 3
A60 X_LCD_DATA00 O VDD_3V3_LOGIC DISP0 data 0
A61 GND - - Ground 0 V
A62 X_LCD_ENABLE O VDD_3V3_LOGIC DISP0 enable
A63 X_LCD_HSYNC O VDD_3V3_LOGIC DISP0 horizontal sync
A64 X_LCD_RESET O VDD_3V3_LOGIC DISP0 reset
A65 X_ENET_REFCLK I VDD_3V3_LOGIC ENET RMII reference clock
A66 GND - - Ground 0 V
A67 X_ENET_TXER O VDD_3V3_LOGIC ENET transmit error
A68 X_ENET_RXD0 I VDD_ENET_IO ENET RMII receive data 0
A69 X_ENET_RXD1 I VDD_ENET_IO ENET RMII receive data 1
A70 X_ENET_RX_ER I VDD_ENET_IO ENET RMII receive error
Table 3: Pinout of the phyCORE-Connector X1, Row A (continued)