Phytec phyCORE-i.MX 6, Hardware Manual

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Pin Description
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PHYTEC Messtechnik GmbH 2016 L-808e_2
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Pin # Signal ST Voltage Domain Description
C38 X_HDMI_CEC I/O VDD_3V3_LOGIC HDMI CEC
C39 X_HDMI_CLKP TDMS_O i.MX 6 internal HDMI clock+
C40 X_HDMI_CLKM TDMS_O i.MX 6 internal HDMI clock-
C41 X_HDMI_D1P TDMS_O i.MX 6 internal HDMI data1+
C42 X_HDMI_D1M TDMS_O i.MX 6 internal HDMI data1-
C43 GND - - Ground 0 V
C44 X_HDMI_DDC_SDA I/O VDD_3V3_LOGIC HDMI DDC data
C45 X_CSI0_DAT18 I VDD_3V3_LOGIC IPU1_CSI0 data 18
C46 X_CSI0_DAT16 I VDD_3V3_LOGIC IPU1_CSI0 data 16
C47 X_CSI0_DAT14 I VDD_3V3_LOGIC IPU1_CSI0 data 14
C48 GND - - Ground 0 V
C49 X_CSI0_DAT12 I VDD_3V3_LOGIC IPU1_CSI0 data 12
C50 X_CSI0_DAT10 I VDD_3V3_LOGIC IPU1_CSI0 data 10
C51 X_CSI0_DAT8 I VDD_3V3_LOGIC IPU1_CSI0 data 8
C52 X_CSI0_DAT6 I VDD_3V3_LOGIC IPU1_CSI0 data 6
C53 X_CSI0_DAT5 I VDD_3V3_LOGIC IPU1_CSI0 data 5
C54 GND - - Ground 0 V
C55 X_CSI0_DAT4 I VDD_3V3_LOGIC IPU1_CSI0 data 4
C56 X_CSI0_PIXCLK O VDD_3V3_LOGIC IPU1_CSI0 pixel clock
C57 X_FLEXCAN1_TX O VDD_3V3_LOGIC FLEXCAN1 transmit
C58 GND - - Ground 0 V
C59 X_LV LVDS_O i.MX 6 internal LVDS0 data 1+
C60 X_LVDS0_TX1- LVDS_O i.MX 6 internal LVDS0 data 1-
C61 X_LV LVDS_O i.MX 6 internal LVDS0 data 0+
C62 X_LVDS0_TX0- LVDS_O i.MX 6 internal LVDS0 data 0-
C63 GND - - Ground 0 V
C64 X_LV LVDS_O i.MX 6 internal LVDS0 data 3+
C65 X_LVDS0_TX3- LVDS_O i.MX 6 internal LVDS0 data 3-
C66 X_LV LVDS_O i.MX 6 internal LVDS1 clock+
C67 X_LVDS1_CLK- LVDS_O i.MX 6 internal LVDS1 clock-
C68 GND - - Ground 0 V
C69 X_LV LVDS_O i.MX 6 internal LVDS1 data 0+
C70 X_LVDS1_TX0- LVDS_O i.MX 6 internal LVDS1 data 0-
Table 5: Pinout of the phyCORE-Connector X1, Row C (continued)