Phytec phyCORE-i.MX 6, Hardware Manual

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LVDS Camera Interface
©
PHYTEC Messtechnik GmbH 2016 L-808e_2
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15.1 Parallel 0 Camera Interface (CSI0 of IPU#1)
The camera interface Parallel 0 (CSI0 of IPU#1) is available at the phyCORE-Connector with
16 data bits, HSYNC, VSYNC and PIXCLK.
The following table shows the location of the Parallel 0 (CSI0 of IPU#1) camera signals at
the phyCORE-Connector.
Pin # Signal ST Voltage Domain Description
X1D40 X_CSI0_DAT19 I VDD_3V3_LOGIC IPU1_CSI0 data 19
X1C45 X_CSI0_DAT18 I VDD_3V3_LOGIC IPU1_CSI0 data 18
X1D41 X_CSI0_DAT17 I VDD_3V3_LOGIC IPU1_CSI0 data 17
X1C46 X_CSI0_DAT16 I VDD_3V3_LOGIC IPU1_CSI0 data 16
X1D43 X_CSI0_DAT15 I VDD_3V3_LOGIC IPU1_CSI0 data 15
X1C47 X_CSI0_DAT14 I VDD_3V3_LOGIC IPU1_CSI0 data 14
X1D44 X_CSI0_DAT13 I VDD_3V3_LOGIC IPU1_CSI0 data 13
X1C49 X_CSI0_DAT12 I VDD_3V3_LOGIC IPU1_CSI0 data 12
X1D45 X_CSI0_DAT11 I VDD_3V3_LOGIC IPU1_CSI0 data 11
X1C50 X_CSI0_DAT10 I VDD_3V3_LOGIC IPU1_CSI0 data 10
X1D46 X_CSI0_DAT9 I VDD_3V3_LOGIC IPU1_CSI0 data 9
X1C51 X_CSI0_DAT8 I VDD_3V3_LOGIC IPU1_CSI0 data 8
X1D47 X_CSI0_DAT7 I VDD_3V3_LOGIC IPU1_CSI0 data 7
X1C52 X_CSI0_DAT6 I VDD_3V3_LOGIC IPU1_CSI0 data 6
X1C53 X_CSI0_DAT5 I VDD_3V3_LOGIC IPU1_CSI0 data 5
X1C55 X_CSI0_DAT4 I VDD_3V3_LOGIC IPU1_CSI0 data 4
X1C56 X_CSI0_PIXCLK O VDD_3V3_LOGIC IPU1_CSI0 pixel clock
X1D48 X_CSI0_VSYNC I VDD_3V3_LOGIC IPU1_CSI0 vertical sync
X1D51 X_CSI0_HSYNC I VDD_3V3_LOGIC IPU1_CSI0 horizontal sync
X1D16 X_CCM_CLKO1 O VDD_3V3_LOGIC
CCM clock output 1 (Camera0
MCLK)
Signals that can be optionally used with the camera ports
X1B23 X_I2C1_SCL
OC_BI VDD_3V3_LOGIC I2C1 clock
X1B24 X_I2C1_SDA OC_BI VDD_3V3_LOGIC I2C1 data
X1D50 X_CSI0_DATA_EN O VDD_3V3_LOGIC IPU1_CSI0 data enable
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X1A38 X_CSI1_DATA00 I VDD_3V3_LOGIC CSI1 data 0 (GPIO3_09)
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Table 29: Camera Interface Parallel 0 (IPU1_CSI0) Signal Location
Using the phyCORE's camera interface Parallel 0, together with an I²C bus facilitates easy
implementation of a CMOS camera interface, e.g. a phyCAM-P or a phyCAM-S+ interface, on
a custom carrier board (
section 15.4 ).
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: Recommended to implement special control features for the camera interface circuitry on the carrier board (e.g.
enabling/disabling of the interface, switching between phyCAM-P and phyCAM-S, etc.). Please refer to L-748 or
appropriate Phytec CB designs as reference.