Phytec phyCORE-i.MX 6, Hardware Manual

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phyCORE
®
-i.MX 6 [PCM-058]
50 ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
On the phyCORE-i.MX 6 SOM camera port IPU1_CSI0 is brought out as parallel interfaces
(Parallel 0) with 16 data bits, HSYNC, VSYNC and PIXCLK. Camera port IPU2_CSI1 is also
available as parallel interfaces (Parallel 1) with 20 data bits, HSYNC, VSYNC and PIXCLK.
The MIPI/CSI-2 interface connects to the phyCORE-Connector with 5-lanes (
Figure 12 )
Figure 12: Camera Interfaces at the phyCORE-Connector (Parallel 0(CSI0 of IPU#1),
Parallel 1(CSI1 of IPU#2), and MIPI/CSI-2)
The camera interfaces of the phyCORE-i.MX 6 include all signals and are prepared to be
used as phyCAM-S(+), phyCAM-P, or MIPI/CSI-2 interface on an appropriate carrier board.
Please refer to
section 15.4 f or more information on how to use the camera interfaces on a
carrier board with different interface options.