Phytec phyCORE-i.MX 6, Hardware Manual

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Tamper Detection
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PHYTEC Messtechnik GmbH 2016 L-808e_2
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16 Tamper Detection
The phyCORE-i.MX 6 supports the tamper detection feature of the i.MX 6. With the tamper
detection feature it is possible to recognize when the device encounters unauthorized
opening, or tampering.
For this purpose, the i.MX 6's Tamper Detection signal is available at pin X1D70 of the
phyCORE-Connector.
When not in use, the Tamper Detection signal is pulled-down internally. In order to
implement tamper protection this signal should be connected to a Tamper Detection
contact in the application which is normally closed pulling the Tamper Detection signal to
the power domain VDD_MX6_SNVS on the phyCORE-i.MX 6 (i.MX 6: VDD_SNVS_IN).
For proper operation of the tamper detection an always-ON power supply (coin cell battery,
or memory backup capacitor) must be connected to the VDD_MX6_SNVS power input at pin
X1A5 of the phyCORE-Connector.
If the tamper detection feature is enabled by software then opening of the tamper contact
can, e.g., result in:
•
switching system power ON with a Tamper Detection alarm interrupt asserted (for
software reaction) , or
•
activating security related hardware (e.g. automatic and immediate erasure of the
Zeroizable Master Key and deny access and erase secure memory contents)
Caution:
To use tamper detection ensure the correct configuration of jumpers J3 and J6. J3 must be
set to 2+3 to connect a backup voltage source to the i.MX 6 low power domain (SNVS_LP).
J6 must be closed at 1+2 to route the TAMPER signal to pin X1D70 of the
phyCORE-Connector.