Phytec phyCORE-i.MX 6, Hardware Manual

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SD / MMC Card Interfaces
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PHYTEC Messtechnik GmbH 2016 L-808e_2
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8 SD / MM Card Interfaces
The phyCORE bus features two SD / MM Card interface. On the phyCORE-i.MX 6 the interface
signals extend from the controllers third and first Ultra Secured Digital (uSDHC3 /
uSDHC1) Host Controller to the phyCORE-Connector.
Table 11 shows the location of the
different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is
fully compatible with the SD Memory Card Specification 3.0 and SD I/O Specification, Part
E1, v1.10. SDC / MMC interface SD3 (uSDHC3 of the i.MX 6), supports 8 data channels and
SD1 (uSDHC1 of the i.MX 6) 4 data channels. Both interfaces have a maximum data rate of
up to 104 MB/s (refer to the
i.MX 6 Reference Manual for more information).
Pin # Signal ST Voltage Domain Description
X1A7 X_SD3_CMD O VDD_3V3_LOGIC uSDHC3 command
X1A8 X_SD3_DATA0 I/O VDD_3V3_LOGIC uSDHC3 data 0
X1A9 X_SD3_DATA2 I/O VDD_3V3_LOGIC uSDHC3 data 2
X1A10 X_SD3_DATA5 I/O VDD_3V3_LOGIC uSDHC3 data 5
X1A12 X_SD3_DATA7 I/O VDD_3V3_LOGIC uSDHC3 data 7
X1A13 X_SD3_RESET O VDD_3V3_LOGIC uSDHC3 reset
X1B7 X_SD3_CLK O VDD_3V3_LOGIC uSDHC3 clock
X1B8 X_SD3_DATA1 I/O VDD_3V3_LOGIC uSDHC3 data 1
X1B9 X_SD3_DATA3 I/O VDD_3V3_LOGIC uSDHC3 data 3
X1B10 X_SD3_DATA4 I/O VDD_3V3_LOGIC uSDHC3 data 4
X1B11 X_SD3_DATA6 I/O VDD_3V3_LOGIC uSDHC3 data 6
X1A14 X_SD1_DATA0 I/O VDD_3V3_LOGIC uSDHC1 data 0
X1A15 X_SD1_DATA2 I/O VDD_3V3_LOGIC uSDHC1 data 2
X1B13 X_SD1_CLK O VDD_3V3_LOGIC uSDHC1 clock
X1B14 X_SD1_CMD O VDD_3V3_LOGIC uSDHC1 command
X1B15 X_SD1_DATA1 I/O VDD_3V3_LOGIC uSDHC1 data 1
X1B16 X_SD1_DATA3 I/O VDD_3V3_LOGIC uSDHC1 data 3
Table 11: Location of the SD / MM Card Interface Signals
The interfaces do not provide dedicated card detect or write protect signals. The card
detect and write protect function can be implemented easily by using four GPIOs of the
i.MX 6.