Phytec phyCORE-i.MX 6, Hardware Manual

Page: 54 / 82

phyCORE
®
-i.MX 6 [PCM-058]
40 ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
9.6 I
2
C Interface
The Inter-Integrated Circuit (I
2
C) interface is a two-wire, bidirectional serial bus that
provides a simple and efficient method for data exchange among devices. The i.MX 6
contains three identical and independent multimaster fast-mode I
2
C modules. The
interface of the first module (I2C1) is available on the phyCORE-Connector.
Note:
To ensure the proper functioning of the I
2
C interface external pull resistors matching the
load at the interface must be connected. There are no pull up resistors mounted on the
module.
The following table lists the I
2
C ports on the phyCORE-Connector.
Pin # Signal ST Voltage Domain Description
B23 X_I2C1_SCL OC_BI VDD_3V3_LOGIC I2C1 clock
B24 X_I2C1_SDA OC_BI VDD_3V3_LOGIC I2C1 data
Table 18: I
2
C Interface Signal Location
The third I
2
C module (I2C3) connects to the on-board EEPROM ( section 7.4 ) and to the
PMIC at U16 ( section 4.2 ).
9.7 I
2
S Audio Interface (SSI))
The Synchronous Serial Interface (SSI) of the phyCORE-i.MX 6 is a full-duplex, serial
interface that allows to communicate with a variety of serial devices, such as standard
codecs, digital signal processors (DSPs), microprocessors, peripherals, and popular
industry audio codecs that implement the inter-IC sound bus standard (I
2
S) and Intel
AC’97 standard. The i.MX 6 provides three instances of the SSI module. On the
phyCORE-i.MX 6 SSI is brought out to the phyCORE-Connector through port 5 of the
i.MX 6's Digital Audio Multiplexer (AUDMUX5).
The main purpose of this interface is to connect to an external codec, such as I
2
S. The
AUDMUX port is intend to be used in synchronous mode (4-wire interface). Hence, the
receive data timing is determined by TXC and TXFS. The four signals extending from the
i.MX 6 SSI module to the phyCORE-Connector are RXD, TXC, TXFS and TXD.
Pin # Signal ST Voltage Domain Description
X1D52 X_AUD5_RXD I/O VDD_3V3_LOGIC AUD5 receive data
X1D53 X_AUD5_TXC I/O VDD_3V3_LOGIC AUD5 transmit clock
X1D54 X_AUD5_TXFS I/O VDD_3V3_LOGIC AUD5 frame sync
X1D56 X_AUD5_TXD I/O VDD_3V3_LOGIC AUD5 transmit data
Table 19: I
2
S Interface Signal Location