Phytec phyCORE-i.MX 6, Hardware Manual

Page: 53 / 82

Serial Interfaces
©
PHYTEC Messtechnik GmbH 2016 L-808e_2
39
9.5 SPI Interface
The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that
provides a simple and efficient method for data exchange among devices. The phyCORE
provides two SPI interfaces on the phyCORE-Connector X1. The SPI interfaces provide one
respectively two chip select signals. The Enhanced Configurable SPI (eCSPI) of the i.MX 6
has five separate modules (eCSPI1, eCSPI2, eCSPI3, eCSPI4 and eCSPI5) which support
data rates of up to 20 Mbit/s. The interface signals of the first and second module (eCSPI1,
eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave
configurable. The following table lists the SPI signals on the phyCORE-Connector.
Pin # Signal ST Voltage Domain Description
X1A22 X_ECSPI1_SCLK O VDD_3V3_LOGIC eCSPI1 clock
X1A23 X_ECSPI1_MOSI I/O VDD_3V3_LOGIC eCSPI1 master output/slave input
X1A24 X_ECSPI1_SS0 O VDD_3V3_LOGIC eCSPI1 chip select 0
22
X1B25 X_ECSPI1_MISO I/O VDD_3V3_LOGIC eCSPI1 master input/slave output
X1A43 X_ECSPI2_MISO I/O VDD_3V3_LOGIC eCSPI2 master input/slave output
X1A44 X_ECSPI2_SS1
O VDD_3V3_LOGIC eCSPI2 chip select 1
22
X1A45 X_ECSPI2_SS0 O VDD_3V3_LOGIC eCSPI2 chip select 0
X1B45 X_ECSPI2_SCLK O VDD_3V3_LOGIC eCSPI2 clock
22
X1B46 X_ECSPI2_RDY I VDD_3V3_LOGIC eCSPI2 data ready
X1B47 X_ECSPI2_MOSI I/O VDD_3V3_LOGIC eCSPI2 master output/slave input
Table 17: SPI Interface Signal Location
Note:
When using the eCSPI1 interface it must be considered that the on-board SPI Flash is
connected to this interface, too. The SPI Flash is accessed through SS1 of module eCSPI1
(
section 7.5 ).
22
: Special care must be taken not to override the device configuration when using this pin as input ( section 6.2 ).