Omron CJ1M-CPU21, Operation Manual

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71
Auxiliary Area Data Allocation Section 4-3
High-speed Counter
1
Overflow/Underflow
Flag
A27509 This flag indicates when an overflow or under-
flow has occurred in the high-speed counter 1
PV. (Used only when the counting mode is set to
Linear Mode.)
0: Normal
1: Overflow or underflow
Read only • Cleared when
power is turned
ON.
• Cleared when
operation starts.
• Cleared when the
PV is changed.
• Refreshed when
an overflow or
underflow occurs.
High-speed Counter
1
Count Direction
A27510 This flag indicates whether the high-speed
counter is currently being incremented or decre-
mented. The counter PV for the current cycle is
compared with the PC in last cycle to determine
the direction.
0: Decrementing
1: Incrementing
Read only • Setting used for
high-speed
counter, valid dur-
ing counter opera-
tion.
High-speed Counter
0 Reset Bit A53100 When the reset method is set to Phase-Z signal
+ Software reset, the corresponding high-speed
counter's PV will be reset if the phase-Z signal is
received while this bit is ON.
When the reset method is set to Software reset,
the corresponding high-speed counter's PV will
be reset in the cycle when this bit goes from
OFF to ON.
Read/write • Cleared when
power is turned
ON.
High-speed Counter
1 Reset Bit A53101 Read/write
High-speed Counter
0 Gate Bit A53108 When a counter's Gate Bit is ON, the counter's
PV will not be changed even if pulse inputs are
received for the counter.
When the bit is turned OFF again, counting will
restart and the high-speed counter's PV will be
refreshed.
When the reset method is set to Phase-Z signal
+ Software reset, the Gate Bit is disabled while
the corresponding Reset Bit (A53100 or
A53101) is ON.
Read/write • Cleared when
power is turned
ON.
High-speed Counter
1 Gate Bit A53109 Read/write
Name Address Description Read/Write Times when data is
accessed