Oki OKIFAX 5950, Maintenance Manual

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R76-
OF5750/5950 Series January 2001 A3 - 1
A3.1 MCNT
A3.1.1 CPU
A3.1.1.1 Functions
A 32-bit RISC CPU is used as a core and it is provided with the following peripheral functions:
• Built-in PROM/Mask ROM
• Built-in RAM
• Bus state controller (DRAM control and chip select creation)
• Interrupt controller
• DMA controller
• 16-bit timer pulse unit
• Serial communication interface
(1) CPU’s throughput
The basic clock frequency is 20 MHz. A program/data is stored in the built-in ROM/RAM.
The rated throughput is 20 MIPS when optimum object code has been created. However,
the actual throughput is reduced due to the access times needed by external devices.
(2) Built-in PROM/Mask ROM
The built-in ROM size is 64 KB and memory addresses range from 000000h to 000FFFh.
(3) Built-in RAM
The built-in RAM size is 4 KB and memory addresses range from FFFF000h to
FFFFFFFh.
(4) Bus state controller
The bus state controller controls the DRAM and accesses the flash ROM and external
devices.
(Figure 6.1 shows the timing chart of the basic bus cycle.)
(5) Interrupt controller
This system has nine interrupts. Three interrupts /IRQ 4, /IRQ6, and /IRQ7 are used but
the other six interrupts /IRQ0 to /IRQ3, IRQ5, and NMI are not used.
Interrupts are allocated as follows:
/IRQ7 = Print-related user timer interrupt
/IRQ6 = Matsushita V.34 modem interrupts 1and 2, Sanyo V.17 modem, encryption, line
ringing tone (Ring), Sanyo read control IC
/IRQ4 = Centronics I/F controller interrupt, JBIG chip interrupt, MUPIS I/F, power I/F,
second tray I/F, user DMA channel 4/5 (Centronics), use DMA channel 6/7
(JBIG)
(6) DMA controller
Two channels of DMAs with external transfer request (DREQ) and acknowledge (DACK)
pins and two channels of DMAs without DREQ/DACK pins are incorporated.
DMA channel 0 (with DREQ/DACK): Used for transfer form read image processing LSI
chip to memory.
DMA channel 1 (with DREQ/DACK): Used for transfer from memory to IOGA print image
processor.
DMA channel 2 (without DREQ/DACK): Not used.
DMA channel 3 (without DREQ/DACK): Used to count main motor operating pulses.