NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 83 / 555

Port Integration Module (S12VRPPIMV1)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 83
output or input of a peripheral module.
2.4.2 Registers
Table 2-39 lists the implemented configuration bits which are available on each port. These registers
except the pin input registers can be written at any time, however a specific configuration might not
become active. For example a pull-up device does not become active while the port is used as a push-pull
output.
Unimplemented bits read zero.
2.4.3 Pin I/O Control
Figure 2-33 illustrates the data paths to and from an I/O pin. Input and output data can always be read via
the input register (PTIx, Section 2.3.3.2, “Port Input Register ”) independent of if the pin is used as
general-purpose I/O or with a shared peripheral function. If the pin is configured as input (DDRx=0,
Section 2.3.3.3, “Data Direction Register ”), the pin state can also be read through the data register (PTx,
Section 2.3.3.1, “Port Data Register ”).
Table 2-39. Bit Indices of Implemented Register Bits per Port
Port Data
Register
Port
Input
Register
Data
Direction
Register
Pull
Device
Enable
Register
Polarity
Select
Register
Port
Interrupt
Enable
Register
Port
Interrupt
Flag
Register
Digital
Input
Enable
Register
Reduced
Drive
Register
Wired-Or
Mode
Register
Port PT PTI DDR PER PPS PIE PIF DIE RDR WOM
E 1-0 — 1-0 PDPEE — — — — — —
S 3-0 3-0 3-0 3-0 3-0 — — — — 3-0
AD 5-0 5-0 5-0 5-0 5-0 5-0 5-0 —
1
1
Digital input enable bits are located in the ADC register ATDDIEN
— —
T 3-0 3-0 3-0 3-0 3-0 — — — — —
P 5-0 5-0 5-0 5-0 5-0 5-0 5-0 — 2-0 —
L — 5-0 — — 5-0
2
2
The PPSL bits select the active interrupt edge. They do not select the polarity of the pull device.
5-0 5-0 5-0 — —