NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 78 / 555

Port Integration Module (S12VRPPIMV1)
MC9S12VRP Family Reference Manual Rev. 1.3
78 NXP Semiconductors
2.3.4.5 Port L ADC Direct Register (PTADIRL)
2.3.4.6 Port L ADC Bypass Register (PTABYPL)
Address 0x0266 Access: User read/write
1
1
Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R 0 0
PTADIRL5 PTADIRL4 PTADIRL3 PTADIRL2 PTADIRL1 PTADIRL0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-25. Port L ADC Direct Register (PTADIRL)
Table 2-31. PTADIRL Register Field Descriptions
Field Description
5-0
PTADIRL
5-0
Port L ADC Direct Connection —
This bit connects the analog input signal directly to the ADC channel, bypassing the voltage divider. This bit takes
effect only in analog mode (PTAENL=1).
1 Input pin directly connected to ADC channel
0 Input voltage divider active on analog input to ADC channel
Address 0x0267 Access: User read/write
1
1
Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R 0 0
PTABYPL5 PTABYPL4 PTABYPL3 PTABYPL2 PTABYPL1 PTABYPL0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-26. Port L ADC Bypass Register (PTABYPL)
Table 2-32. PTABYPL Register Field Descriptions
Field Description
5-0
PTABYPL
5-0
Port L ADC Connection Bypass —
This bit bypasses and powers down the impedance converter stage in the signal path from the analog input pin to
the ADC channel input. This bit takes effect only if using direct input connection to the ADC channel (PTADIRL=1).
1 Impedance converter bypassed
0 Impedance converter used